A register file is a small, fast array of registers with several access ports. A CPU-style file serves two reads and one write in the same cycle, with fixed rules for collisions and for the zero register.
Read it left to right: one write enters the array at the clock edge, and two independent reads leave it in the same cycle. Each read port costs a 32-to-1 mux; the bypass added in the second lesson sits after those muxes.
Question | Flop array | SRAM bank |
|---|---|---|
Small file (illustratively tens of words) | Resettable; read mux and routing cost grows with ports | Macro/block overhead may dominate; compare mapped area |
Large table (illustratively hundreds of words) | Area grows with every flop and every read mux | May be denser; dimensions and replication can require several blocks |
Two reads plus one write in one cycle | Two muxes on one array | Needs replication or a true multi-port macro |
Reset to a known state | A loop clears the array (fine for flops) | No array reset; write zeros with a state machine |
3 lessons, about 11 min
Word counts here are illustrative, not break-even thresholds. Compare candidates at the same width, 2R1W throughput, reset/x0/bypass contract and required read latency. Record target/library and tool settings, mapped flop/LUT/RAM counts or cell area, replication and bypass cost, and timing at the required clock. A synchronous bank that adds a cycle is an architectural alternative requiring pipeline changes, not an equivalent drop-in. No mapped area or timing results are supplied here; physical timing signoff is separate.
At 32-bit width it needs 1024 storage bits plus two read muxes, and supports combinational reads and reset. Compare mapped candidates on the chosen target; depth alone cannot decide the winner. Banks must meet the port, latency and collision contract, including replication and bypass overhead.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Multi-Port Register File Fundamentals
2R1W means two combinational reads and one clocked write in the same cycle.
By contract, a same-cycle read of the written register returns the write data. Register x0 reads zero and drops writes.
Synchronous SRAM banks cannot clear every word at once, and they change the read latency.
Rule of thumb: fix read-during-write and x0 in the contract first, then write the code.
2R1W Register File with Bypass
Each read port selects the write data when write enable is high and the write address matches.
A bypass keyed on the address alone forwards stale write data on idle cycles.
The bypass covers only the same-cycle case. A writeback one stage later needs pipeline forwarding.
Read-During-Write Hazards and Assertions
The property: write enabled, write address equals read address and is nonzero, then read data equals write data.
Without the nonzero guard the property fails on every write while x0 is read, because x0 reads zero.
Check during the write cycle, before the edge commits the write. A check after the edge proves nothing about bypass.
Mini project: a two-master bus with decoder, default slave and timeout
Practice question: Register file with two read ports and one write port
Practice question: Multi-port register file (3+ ports)
Code lab: 2x8 register file
Practice question: 2R1W register file: read-first vs write-first semantics
Interview: run a mock interview on this topic