AXI-Stream transfers payload beats without addresses. A beat moves across the interface exactly when TVALID and TREADY are both 1.
Rule | Meaning |
|---|---|
Beat transfer | A beat is accepted on the clock edge where |
Packet end | An accepted beat with |
Backpressure | Either side can stall. Nothing moves unless both signals are 1. |
3 lessons, about 11 min
One beat. A transfer needs both signals at 1 on the same edge, so only the middle cycle moves data.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Core AXI-Stream Signals
A transfer is TVALID && TREADY at a clock edge. A packet ends on the beat where TVALID, TREADY and TLAST are all 1.
Once offered, TVALID, the valid TDATA bytes, TKEEP and TLAST stay stable until acceptance.
The source drives TVALID without waiting for TREADY. The sink drives TREADY and may wait for TVALID.
A Stream Pipeline Register
A single full flag is the whole control, and s_tready = !full || pop.
The push branch runs first, so a coincident arrival replaces the departing beat and the stage stays lossless.
The forward payload is registered, but ready is combinational. Use the skid buffer when backpressure must be registered.
Packets, TLAST, TKEEP and Monitors
A packet is the run of beats up to and including TLAST. Only an accepted beat can close it.
TKEEP bit i covers byte i. General AXI-Stream allows sparse and all-zero TKEEP, and a zero-byte TLAST beat still ends the packet.
Check stalls with !== so a known-to-X change is caught, and use $isunknown on TKEEP.
Mini project: a two-master bus with decoder, default slave and timeout
Code lab: AXI stream handshake
Code lab: Pipeline register stage
Interview: run a mock interview on this topic