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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
    • SRAM and ROM
    • Register Files
    • Valid/Ready Handshake
    • AXI-Lite
    • AXI-Stream
      • Core AXI-Stream Signals
      • A Stream Pipeline Register
      • Packets, TLAST, TKEEP and Monitors
    • Bus Integration
    • Synchronous FIFO
    • Register-Map and CSR RTL
    • Memory Reliability
    • Peripheral RTL Integration
    • Full AXI4: RTL Roadmap
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
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‹AXI-Stream
  1. Topics
  2. RTL Design
  3. Memory & Buses
  4. AXI-Stream
  5. Core AXI-Stream Signals

Part 7 · Memory & Buses · Intermediate

Core AXI-Stream Signals

TDATA, TVALID, TREADY, TLAST and TKEEP: the beat rule, the packet-end equation, and a signal table.

On this page

    Why this matters

    AXI-Stream carries beats with no addresses, so a counter that increments on TVALID alone overcounts every stall. One equation defines a transfer, and TLAST marks where a packet ends.

    After this lesson you can: write the transfer and packet-end equations, and state who drives each signal and what must hold during a stall.

    Beats without addresses

    AXI-Stream carries a flow of payload beats. There are no addresses, so position in the stream gives each beat its meaning.

    The source offers a beat with TVALID. The sink shows it can accept with TREADY. The beat transfers on the edge where both are 1.

    The signals

    Signal

    Driven by

    Meaning

    TDATA

    Source

    Payload word. Meaningful while TVALID is 1.

    TVALID

    Source

    A beat is available.

    TREADY

    Sink

    The sink can accept a beat this cycle.

    TLAST

    Source

    This beat ends the packet.

    TKEEP

    Source

    One bit per byte. A 1 means the byte is valid.

    TSTRB, TID, TDEST and TUSER also exist in the standard. They mark sparse byte lanes, stream IDs, destinations and user sideband. This topic leaves them out of scope.

    The two equations

    Two Boolean relations identify transfers and packet ends. They require the temporal offer/hold rules as well.

    Diagram
    fire    = TVALID && TREADY
    pkt_end = fire && TLAST

    A packet ends on the beat where TVALID, TREADY and TLAST are all 1. Count transfers, not levels: only edges with fire = 1 move data.

    TVALID

    TREADY

    TLAST

    fire

    pkt_end

    What happens at the edge

    0

    0

    any

    0

    0

    Nothing offered, sink busy

    0

    1

    any

    0

    0

    Sink waits; TLAST means nothing without TVALID

    1

    0

    0

    0

    0

    Stall: the source holds the beat

    1

    0

    1

    0

    0

    Stall on the last beat: the packet is not over yet

    1

    1

    0

    1

    0

    A beat transfers; the packet continues

    1

    1

    1

    1

    1

    The last beat transfers; the packet ends

    Read each row as one clock edge. Only the last two rows move data, and only the very last closes a packet. The testbench below checks all eight input combinations against these columns.

    The source asserts TVALID when a beat is available without waiting for TREADY. Once offered, TVALID remains asserted and TDATA's valid bytes, TKEEP and TLAST stay stable until acceptance, including the accepting edge. The sink may wait for TVALID before asserting TREADY. See Rules That Keep Flow Control Safe for the shared handshake rules.

    Common mistakes

    Common pitfall

    Counting beats on TVALID alone overcounts through every stall. Gate each counter, scoreboard and state advance with TVALID && TREADY.

    Interview

    Likely question: “when does a transfer happen”. Answer: on the clock edge where TVALID and TREADY are both 1. TLAST on that beat ends the packet.

    Check yourself What is fire when TVALID is 1 and TREADY is 0?

    Zero: no transfer happens. The source must hold TDATA, TKEEP and TLAST stable until the sink is ready.

    Check yourself Which three signals are 1 on the last beat of an accepted packet?

    TVALID, TREADY and TLAST. All three together mark the packet end.

    Check yourself Which side drives TREADY, and what does 0 mean?

    The sink drives it. A 0 means it cannot accept a beat this cycle, so the offered payload must hold.

    Testbench

    The two equations plus a testbench that checks all eight input combinations.

    axis_fire.sv
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    module axis_fire (
      input  logic tvalid,
      input  logic tready,
      input  logic tlast,
      output logic fire,
      output logic pkt_end
    );
      assign fire = tvalid && tready;
      assign pkt_end = fire && tlast;
    endmodule
    
    module tb_axis_fire;
      logic tvalid, tready, tlast, fire, pkt_end;
      axis_fire dut (.*);
      int errors = 0;
      initial begin
        for (int i = 0; i < 8; i++) begin
          tvalid = i[2]; tready = i[1]; tlast = i[0]; #1;
          if (fire !== (tvalid && tready)) errors++;
          if (pkt_end !== (fire && tlast)) errors++;
        end
        if (errors == 0) $display("PASS: fire and packet-end equations hold for all 8 input combinations");
        else $display("FAIL: %0d errors", errors);
        $finish;
      end
    endmodule

    Remember

    • A transfer is TVALID && TREADY at a clock edge. A packet ends on the beat where TVALID, TREADY and TLAST are all 1.

    • Once offered, TVALID, the valid TDATA bytes, TKEEP and TLAST stay stable until acceptance.

    • The source drives TVALID without waiting for TREADY. The sink drives TREADY and may wait for TVALID.

    Keep going

    • Code lab: AXI stream handshake

    • Interview: run a mock interview on this topic

    Related topics

    • A Stream Pipeline Register

    • Packets, TLAST, TKEEP and Monitors

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    See also

    • Packets, TLAST, TKEEP and Monitors