Conventional FPGA block RAM and selected synchronous SRAM macros expect an array, a clocked write, and a synchronous read with no array reset. SRAM as a category also includes asynchronous-read resources. Density and speed relative to flip-flops depend on depth, width, ports, latency and target; compare mapped implementations before choosing.
Read the two halves as two netlists for the same RTL behaviour. The left one is what the coding rules in this topic aim for; the right one is what the synthesiser builds when the code breaks a rule.
Left: the array and its read register sit inside one block. That only works if the read is clocked and the array is never reset.
Right: every word becomes its own register and the read becomes a wide mux. An array reset (ram_reset in the next lesson) forces this, because a RAM block cannot clear all its words in one cycle.
6 lessons, about 25 min
That resource requires a clocked read interface. An asynchronous-read contract instead needs a compatible resource, such as supported distributed RAM or flip-flops; other SRAM technologies may provide asynchronous reads.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Inference Starts from Coding Style
Write synchronously with an enable, read into a register, and never reset the array.
Reset the control logic around the memory. To clear contents, run a short state machine after reset.
A generic memory cell in the Yosys output is not proof of a mapped block RAM. Check the target-specific report.
Rule of thumb: read the synthesis report and look for a RAM of the expected size, not thousands of flops.
Single-Port Synchronous RAM Template
Data appears one cycle after the address, so a valid bit must travel with the request.
A write to the address being read shows the old word on dout (read-first); the new word appears on a later read.
A clocked consumer sees the result one edge after dout updates.
Rule of thumb: wrap the RAM so the rest of the design never assumes its latency.
Read-First vs Write-First
The modes differ in one slot only: a read in the same cycle, at the same address, as the write.
Any mode returns the new data for a read issued after the write.
The mode is part of the RAM's contract. An unsupported mode costs a bypass mux and comparator.
Rule of thumb: choose the mode the design needs first, then check the target provides it natively.
Dual-Port RAM Patterns
Use a simple dual-port RAM when one side only writes and the other only reads: it is smaller, faster and has fewer collision cases.
Across two clocks, a read of an address being written is undefined. The async FIFO avoids it by keeping the pointers apart.
Wide RAMs and unusual port-width ratios can need several blocks or a vendor template.
True Dual-Port RAM and Collisions
A same-cycle write to one address is undefined in hardware and not portable.
Prevent it by arbitration or address partitioning, or define it in a wrapper with a priority port and a collision flag.
A collision-safe wrapper needs one clock for both ports, and the address comparator can become the critical path.
Rule of thumb: never leave a collision undefined: prevent it, or define the winner and raise a flag.
ROM Inference
An array with a synchronous read maps to a block ROM. A combinational read becomes logic.
A tiny table, such as four entries, is cheaper as a case than as a memory block with its overhead.
On an FPGA the initial contents go into the bitstream. On an ASIC the ROM macro is a separate cell.
Rule of thumb: generate the table from a function or a file, because hand-typed numbers rot.
Mini project: a two-master bus with decoder, default slave and timeout
Practice question: Asynchronous read memory design in SystemVerilog
Code lab: SRAM model 16x8
Practice question: Single-port RAM with write-first behaviour
Practice question: Dual-port RAM with read-after-write handling
Code lab: Simple dual-port RAM
Interview: run a mock interview on this topic