The write-write collision

Two ports writing the same address in the same cycle is a collision. A hardware RAM gives an undefined result: either value, a mix of bits, or a corrupted word.

The behaviour differs between devices, so a design that causes collisions is not portable. Prevent them at the system level, or make them defined in a wrapper.

Handling collisions

A priority mux makes the RAM slower: the write-enable path now includes an address comparator. If the RAM runs at the limit of its clock, the collision logic can be the critical path.

Move the comparison into the control logic one cycle earlier if necessary.

Same-port read-during-write mode and opposite-port collision behaviour are separate contracts. A common clock alone does not make the opposite port's read valid: AMD block RAM returns old data in the supported READ_FIRST configuration, but the opposite read can be invalid when the writing port uses WRITE_FIRST or NO_CHANGE. The wrapper below specifies old-data reads on both ports; mapping it to a macro requires that exact common-clock cross-port guarantee, or explicit forwarding/collision exclusion.

Port A wins, cycle by cycle

The wrapper below makes the collision defined. Here it runs a short directed sequence in which every access goes to address 5, which starts at 0x00.

Each slot is one clock cycle. A request offered in a slot lands at the edge that ends it, so mem5 (the word at address 5) and doutb change one slot later.

• Slot 0: port A writes 0x11 and port B writes 0x22 to the same word. collision is high, and in slot 1 the word holds 0x11: port A won.

• Slot 2: only port B writes, 0x33. It succeeds, and mem5 is 0x33 in slot 3.

• Slot 3: port A writes 0x44 while port B reads. doutb in slot 4 is the old word 0x33, and the new word 0x44 reaches it in slot 5.

Testbench

A common-clock wrapper where port A wins competing writes and both read outputs return old data. The testbench checks the winner and both directions of cross-port read/write collision. These RTL checks do not establish a physical macro's collision mode; review its configuration and implementation report separately.

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// True dual-port RAM that makes the write-write collision DEFINED: port A wins, and a flag is raised.
module ram_tdp_safe #(parameter int AW = 4, parameter int DW = 8) (
  input  logic          clk,                                      // one clock for both ports (typical for a collision-safe design)
  input  logic          wea, web,
  input  logic [AW-1:0] addra, addrb,
  input  logic [DW-1:0] dina, dinb,
  output logic [DW-1:0] douta, doutb,
  output logic          collision                                 // both ports write the same address in the same cycle
);
  logic [DW-1:0] mem [2**AW];
  assign collision = wea && web && (addra == addrb);

  // Requires a target with common-clock old-data reads on BOTH ports during a collision.
  always_ff @(posedge clk) begin
    if (wea) mem[addra] <= dina;
    if (web && !(wea && addra == addrb)) mem[addrb] <= dinb;       // on a collision port A wins
    douta <= mem[addra];
    doutb <= mem[addrb];
  end
endmodule

Related topics

• ROM inference