SPI, I2C, UART, GPIO, timers, and DMA engines differ at their pins but share an integration shell. This topic teaches that shell and links protocol-specific behavior to the dedicated Protocols course.
A planned SPI sensor-controller integration exercise carries the discussion: CSRs program transfers, a TX FIFO feeds the serializer, an RX FIFO captures samples, DMA moves bursts, and sticky status reports faults. This topic supplies contracts, snippets and worked traces, not a complete controller or executed integration scenario.
5 lessons, about 17 min
It couples pin-level behavior to one bus, mixes independent state machines, and makes verification harder. A thin adapter and CSR contract keep the engine reusable.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Peripheral Shell
The engine sees accepted FIFO operations and start events, never bus channel levels.
engine_busy has a single owner, including the reservation on the accepting edge.
An invalid operation returns an error and is never reported as success.
Rule of thumb: decide who owns each piece of state, then draw the boundary around it.
Clock, Reset, and Power Contract
On reset, drive outputs to protocol-safe values and release the bus side only when its clock is alive.
Do not gate the engine clock while it is busy, a FIFO must drain, or an event capture is pending.
Synchronise asynchronous inputs before control logic uses them.
Rule of thumb: idle hardware can still hold state software must see.
Interrupts and Events
Level causes (watermark, FIFO space) are cleared by removing the condition. Sticky causes (done, timeout, error) are cleared by W1C.
A pulse shorter than the destination sampling gap can be missed by a two-flop synchroniser.
Repeated events merge into one sticky bit. Count them if occurrences matter.
Rule of thumb: software clears sticky bits and removes level causes.
FIFO and DMA Boundary
The request sets at one watermark and clears at the other. Keep the low mark below the high mark, or the hysteresis disappears.
A fall-through wiring needs the front word stable until an accepted pop. A registered-pop FIFO needs a prefetch adapter first.
Software and DMA need arbitration so they cannot pop the same word.
Rule of thumb: count only accepted valid/ready beats, never the request.
Errors and Integration Signoff
A timeout gives one upstream error. The slot stays owned until the late reply drains or a coordinated reset starts a new epoch.
Keep separate ledgers for upstream and downstream accepted work.
Recovery means safe pins, resolved ownership and acceptance of a later legal transfer.
Rule of thumb: never reuse an owned slot because a timeout fired.
Mini project: a two-master bus with decoder, default slave and timeout
Practice question: Memory-mapped register interface with read and write support
Practice question: Reset strategies in RTL: synchronous, asynchronous and gated
Practice question: CDC synchroniser for a memory-peripheral transfer
Code lab: Interrupt aggregator
Code lab: DMA controller FSM
Interview: run a mock interview on this topic