Reset pin outputs and output enables to protocol-safe values.
Release the bus/CSR side only when its clock is alive.
Synchronize asynchronous external inputs before control logic uses them.
Do not gate the engine clock while busy, while FIFO state must drain, or while an interrupt update is pending.
Retain or reinitialize software-visible configuration according to the power-state contract.
Applied to the sensor controller, reset deasserts chip select and drives the serial clock to its configured idle polarity before the engine can start. Clock gating waits until no transfer, FIFO update, or pending event capture needs the engine clock.
State | Required behavior |
|---|---|
Reset asserted | Pins safe, requests low, FIFOs logically empty |
Clock gated | No pending accepted work; wake condition remains observable |
Power off | Outputs isolated; incoming requests blocked |
Wake | Clock stable, reset released, retained/default configuration valid before enable |
Read each arrow as a condition that must already be true before the move.
Run to Gated is the risky edge: a transfer, a FIFO update or an event capture still needing the clock blocks it.
Wake is a state of its own. Enabling the engine before the clock is stable and the configuration is valid is the classic wake-up bug.
The engine is quiescent, no accepted transaction needs progress, FIFO policy is satisfied, and wake/interrupt logic remains clocked or asynchronous by design.