Peripheral events such as RX-not-empty, TX-below-watermark, transfer-done, timeout, and protocol-error have different persistence. Convert them into explicit level or sticky status before aggregation.
The sensor controller uses RX watermark and TX space as level conditions, while transfer-done, timeout, and illegal-command events become sticky pending bits. That distinction determines whether software clears a latch or removes an underlying condition.
Source | Recommended form |
|---|---|
RX data available | Level from FIFO occupancy |
TX space available | Level from watermark |
Transfer done | Sticky edge event |
Timeout/error | Sticky event with diagnostic context |
External pin edge | Synchronized edge detector then sticky pending |
Level causes reassert immediately after software clears them if the underlying condition remains true. Sticky edge causes remain pending until W1C acknowledgement.
An external pin edge first needs a capture contract. A 2FF synchronizer plus edge detector can miss a pulse that rises at 2 ns and falls at 8 ns between destination samples at 0 and 10 ns: both samples see zero, so pending never sets. Stretch high across at least two destination sampling opportunities with setup/hold margin and a similarly observable low gap; a raw asynchronous pin may need a source latch/acknowledged capture. Toggle capture requires that successive toggles be separated enough for the destination to observe each state; otherwise two toggles cancel. For unbounded destination stalls use an acknowledged event transfer and source buffering/backpressure.
Compare the missed 2..8 ns pulse with a stretched 2..28 ns level: ideal samples at 10/20 ns see high and the synchronized edge eventually sets pending. Physical synchroniser reliability, timing margins and reset history still need implementation checks. After capture, repeated events can still coalesce in one sticky bit; use counters or FIFO service when occurrences must be counted.
Each slot is 2 ns. Slot 0 is the reset state, and the destination clock rises at slots 5, 10 and 15, which are the 10, 20 and 30 ns samples.
The short pulse is high in slots 1 to 3 only. Both destination samples see 0, so the first synchronizer never captures it and its pending bit stays 0.
The stretched level stays high from slot 1 to slot 13. The 10 ns sample captures it into the first flop and the 20 ns sample moves it to the second flop.
The sticky pending bit rises after the 30 ns edge, driven only by the stretched side. A second event would still merge into the same bit.
Because it is a level condition and the FIFO still contains data. The correct service action is to drain data below the threshold, not merely clear a bit.