A bus transports reads and writes; the CSR block defines what those accesses mean. Keeping CSR semantics independent from AXI-Lite or APB makes the register bank reusable and keeps software-visible behavior stable when the transport changes.
The lessons build one packet-processor register bank from specification to generated artifacts. CONTROL starts work, STATUS captures completion and faults, a 64-bit LIMIT value commits atomically, and IRQ registers notify software. Later lessons preserve that same behavior behind AXI-Lite and APB.
9 lessons, about 32 min
W1C is field semantics, not transport semantics. Keeping it in the CSR block makes the same register map work behind AXI-Lite, APB, or a test port.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
CSR Contract and Address Map
Compare the whole implemented word address. Unmapped and misaligned accesses return an error and have no side effect.
Reserved bits read zero and ignore writes, so hardware can use them later.
Side effects happen once, on the accepted request, never on a raw bus level.
Rule of thumb: the register map is an interface: every reset value and error response is written down once.
Field Access Types
Access type belongs to the field, not the register.
A W1C write is a clear mask: only written ones acknowledge, and the write must target this register.
Read-clear is dangerous when a debugger or a speculative master can read. Prefer W1C.
Rule of thumb: state what wins when hardware sets and software clears the same bit.
Hardware/Software Arbitration
Status and interrupt bits normally use set-wins: clearing an old event must not erase a new one.
Set-wins keeps one pending cause. It does not count occurrences.
Use one equation for the STATUS view and the interrupt view, so they cannot disagree.
Rule of thumb: write the collision policy in the spec, not in the code comments.
Byte Strobes and Partial Writes
Expand the strobes once, and feed the same mask to every register.
RW fields update only where the mask is set.
W1C clears need both wdata and wstrb.
Atomic and Shadowed Updates
Write the words into shadow registers, then copy the whole shadow into the active value on an explicit commit.
A word counts as written only when a byte strobe is set. Unselected shadow bytes keep their old value.
For a counter wider than the bus, reading the low word snapshots the full value for the high-word read.
Rule of thumb: never let hardware see a partly written multi-word value.
Interrupt Register Pattern
Pending is sticky, so a one-cycle event survives software latency.
Enable controls notification, not capture. The level output stays high until every enabled cause is cleared.
Two events before a clear give one pending bit. Use a counter or a FIFO if each occurrence matters.
Rule of thumb: give the interrupt controller a level that stays high until the cause is acknowledged.
Adapter and Signoff
The adapter converts an accepted transfer into one internal request. Wait cycles are not new requests.
Hold the response until the bus accepts it, with no second side effect while it waits.
Test field semantics without any bus, and the adapter with protocol checks.
Rule of thumb: keep protocol timing in the adapter and register meaning in the CSR bank.
Generated Register Workflow
One machine-readable source, a pinned generator version, and a failing CI check on any uncommitted regeneration diff.
Generated files are build products. Never hand-edit them and leave the schema stale.
The generator does not decide collision priority, read-clear hazards, atomic groups or security access.
Rule of thumb: generate the registers, then still review the semantics.
The Firmware Side: a C Driver for W1C, RC and Shadow Registers
Acknowledge W1C status by writing back only the bits you handled. Never |=, never write back the whole snapshot.
Read an RC register once and keep the value; a second read, or a debugger, sees what is left.
volatile goes in the accessors so every register access happens; check shadow_valid after a commit and bound every poll.
Rule of thumb: on a W1C register, the only value firmware writes is the set of causes it has just serviced.
Mini project: a two-master bus with decoder, default slave and timeout
Practice question: Memory-mapped register interface with read and write support
Code lab: GPIO direction register
Practice question: AXI4-Lite slave with read-only and write-only register access
Code lab: Maskable interrupt register
Practice question: AXI4 write channel with write strobe (WSTRB) support
Interview: run a mock interview on this topic