At this point the packet-processor fields are fully defined without a bus. The adapter's only job is to convert an accepted AXI-Lite or APB transfer into the same internal request and return the same response.
Adapter responsibility | CSR responsibility |
|---|---|
Handshake and channel ordering | Address decode and field behavior |
Capture address/data/strobes | Read mux and write effects |
Return protocol response | Return data and error response |
CSR | Raise |
Timeout at integration boundary | No hidden protocol state |
Use the single-outstanding contract and canonical field map from CSR Contract and Address Map. AXI-Lite captures AW and W independently, pairs them, emits one req_take, then retains B until BREADY. Reads retain RDATA/RRESP until RREADY. APB latches the ACCESS request, issues it once using an issued flag, and asserts PREADY only when its captured CSR response is available. The issued flag resets only on APB completion/new transfer, not on each wait cycle. An APB wait is not another CSR operation.
PSEL is high for the whole transfer and is not drawn. The page's edges E0 to E3 end slots 0 to 3, and the trace starts with enable = 1 and busy = 0. Address and data stay stable through E3.
Slot 0 (E0): PENABLE is low, so this is the setup phase. The adapter latches the address and data.
Slot 1 (E1): access phase, PREADY low. req_take is high for this one cycle, so the CSR sees one request. issued sets and the START count becomes 1.
Slot 2 (E2): still waiting. issued is already 1, so req_take stays low and nothing is replayed. The adapter captures the CSR response.
Slot 3 (E3): PREADY is high and the transfer completes once. issued clears one slot later, and the count stays at 1.
Start with the sticky bit at 1 and a new event arriving at E1. The snapshot at req_take is the old value, and the next sticky value is (old & ~1) | event, so the new event survives the clear. The read response is held until RREADY, and no second clear happens while it waits.
Edge | What happens | RVALID | RREADY | RDATA | Sticky after |
|---|---|---|---|---|---|
E0 | AR accepted and buffered | 0 | - | - | 1 |
E1 |
| 0 | - | - | 1 |
E2 | Response held, stalled | 1 | 0 | 1 | 1 |
E3 | Response held, stalled; no second clear | 1 | 0 | 1 | 1 |
E4 |
| 1 | 1 | 1 | 1 |
A later read sees the new event. RC is not part of the canonical W1C map.
Adapter checker obligations: count req_take and side effects per upstream transaction (each at most one); accepted requests = retired responses + owned responses within a reset epoch; compare saved response data/error on every stalled and accepting edge. Bound response waits in the harness and terminate failures fatally.
Reset values and reserved bits.
Every access type with zero, one, and all-one writes.
Each byte-strobe combination.
Hardware set colliding with software clear.
Unmapped and misaligned accesses.
Back-to-back reads/writes and adapter backpressure.
Interrupt event, mask, enable, clear, and reassertion.
All field semantics can be exhaustively tested without AXI/APB timing, while protocol VIP verifies the adapter separately. Failures localize to transport or register behavior.
The APB and AXI traces on this page are written by hand from the stated contract. They are not output from a run of a complete adapter.