One register, two owners

Sticky status commonly receives a hardware set and software clear on the same edge. The specification must decide whether the event remains pending.

The packet processor uses set-wins for STATUS.done and STATUS.error, so software cannot erase a newly arriving completion or fault while acknowledging an older one.

Each slot is one clock cycle, and an input takes effect at the edge that ends its slot. status_sw uses set-wins and status_cw uses clear-wins; both see the same inputs.

• Slot 1: a hardware set alone. Both bits are 1 from slot 2.

• Slot 3, the collision: set and clear arrive together. Set-wins stays 1; clear-wins drops to 0 in slot 4, and the new event is lost.

• Slot 4: a clear alone. Set-wins now clears too, in slot 5.

Interrupt and error status normally use set wins: software clearing an old event must not erase a new event arriving simultaneously.

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// snippet: set-dominant sticky status
logic [N-1:0] sw_clear;
assign sw_clear = csr_write && addr_hit ? wdata[N-1:0] & write_mask[N-1:0] : '0;
always_ff @(posedge clk or negedge rst_n)
  if (!rst_n) status_q <= '0;
  else        status_q <= (status_q & ~sw_clear) | hw_event_i;

Related topics

• Byte strobes and partial writes