The register specification is an interface

This is the canonical field-level map used by the decoder, driver and expected-value model. All stored fields reset to zero; busy reflects reset-idle hardware. All unlisted bits read zero and ignore writes. Writes apply only strobed bytes; reads return the pre-operation snapshot.

LIMIT active and shadow reset to zero. A successful commit retains shadow data, so later partial writes preserve bytes from that value. The single-request map uses a separate commit write; the helper below also supports final-word-plus-commit for a wider internal caller. RC and W1S examples are teaching variants, not additional mapped fields. Disabled/busy START returns an error and sets config_error; unmapped/misaligned requests return error and no register side effect.

• Addresses are naturally aligned.

• Unmapped reads return zero plus an error response; unmapped writes have no effect.

• Reserved bits read as zero and ignore writes.

• Every reset value is visible to both RTL and software documentation.

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// snippet: transport-independent CSR request
typedef struct packed {
  logic        write;
  logic [11:0] addr;
  logic [31:0] wdata;
  logic [3:0]  wstrb;
} csr_req_t;

typedef struct packed {
  logic [31:0] rdata;
  logic        error;
} csr_rsp_t;

Concrete internal transport: one outstanding request total, req_take = req_valid && req_ready at a rising edge. The adapter holds request payload stable through that edge. The CSR bank captures read data/error and performs all side effects exactly once on req_take; it raises registered rsp_valid after that edge and holds response payload through rsp_valid && rsp_ready. req_ready stays low until the response retires (no same-edge replacement). sw_write, csr_write, wr_lo/wr_hi and command pulses below mean decoded req_take, never raw bus levels. Reset flushes the owned request/response epoch under coordinated adapter reset. RC variants capture old data and clear on req_take, with simultaneous hardware set winning; response delivery never clears again.

Each slot is one clock cycle, and a request is taken at the edge that ends its slot. The first read is CONTROL, which returns 5 (enable 1, mode 2); the second is STATUS, which returns 2 (done).

• Slot 0: req_valid and req_ready are both high, so the CONTROL read is taken at the edge ending slot 0.

• Slots 1 to 3: the response is valid with data 5. rsp_ready is low in slots 1 and 2, so the response is held, and req_ready stays low: the STATUS read waits.

• Slot 3: rsp_ready is high, so the response retires at the edge ending slot 3. req_ready rises only in slot 4, never on the retiring edge.

• Slot 4: the STATUS read is taken; its response 2 is valid and ready in slot 5 and retires.

Related topics

• Field access types

• Address decode