Type | Software write | Hardware update | Typical use |
|---|---|---|---|
RW | Replaces selected bits | Optional | Configuration |
RO | Ignored | Sets current value | Live status |
W1C | Writing 1 clears; 0 holds | Sets sticky events | Error/interrupt status |
W1S | Writing 1 sets; 0 holds | May clear | Command latch |
RC | Internal read acceptance snapshots then clears | Sets event (set wins) | Read-to-acknowledge status variant |
Pulse | Accepted write produces one-cycle pulse | Not stored | Start/flush command |
Read each result row against the top row: outlined bits are the ones the write changed. All four byte strobes are set here.
RW: the field becomes the write data. Four bits change.
W1C: only bits 5 and 2 clear. They are 1 in both the old value and the data. A 1 written over a 0 does nothing, and a 0 never clears.
W1S: only bits 6 and 0 set. Bits that were already 1 stay 1.
In the running block, CONTROL.enable is RW, CONTROL.start is a pulse, STATUS.busy is RO, and STATUS.done/error are W1C sticky fields. Keeping those semantics field-specific avoids ambiguous labels such as treating an entire mixed register as simply RW.
// snippet: common field equations
wire [N-1:0] sw_clr = (sw_write && addr_hit) ? (wdata[N-1:0] & write_mask[N-1:0]) : '0;
rw_q <= (sw_write && addr_hit) ? ((rw_q & ~write_mask) | (wdata & write_mask)) : rw_q;
w1c_q <= (w1c_q | hw_set) & ~sw_clr;
w1s_q <= (w1s_q | sw_clr) & ~hw_clear;
start_p_o <= sw_write && addr_hit && write_mask[START_BIT] && wdata[START_BIT];The shared sw_clr mask is zero unless a write actually targets this register, so stale wdata can never clear or set a sticky bit. This generic equation favours clear and can erase a simultaneous new cause; the canonical STATUS/IRQ map instead uses the set-wins form in the next lesson. Set-wins preserves a simultaneous pending cause, not an occurrence count.
Read-clear is dangerous when a debugger, speculative master, or mirrored software reader can issue reads. Prefer explicit W1C acknowledgement unless the system contract guarantees a single intentional reader.
The tool starts on the example above as a W1C field: it holds 000000AC (1010 1100) and the write data is 00000065 (0110 0101), with all four byte strobes set, so bits 5 and 2 would clear.
Loading register field tool…
Press Write: the field becomes 00000088. Press it again and nothing clears, because bits 5 and 2 are already 0: repeating a W1C acknowledgement is harmless.
Choose RW and the result is 00000065, four bits changed; choose W1S and it is 000000ED, with only bits 6 and 0 set.
Choose RC and press Read twice: the first read returns the value and clears the field, the second returns 00000000. That second read is what a debugger costs you.
The write data is a clear mask. Only written ones acknowledge events; zero means no action.
sw_write=1, addr_hit=0, and every byte strobe is set. Does this RW field change?No. Both the accepted write and this register's address hit must qualify the RW update. Without addr_hit, a write elsewhere would overwrite this field with unrelated write data.