Step | Course/resource |
|---|---|
Handshake foundation | RTL Valid/Ready and AXI-Lite |
Burst, IDs, ordering | Protocols: AXI Channels & Transfers |
Bandwidth and outstanding depth | Protocols: Bandwidth & Latency Budgeting |
Interconnect integration | Protocols: AMBA Integration Debug |
RTL implementation | A scoped master/slave with explicit support matrix |
Verification | AXI VIP + memory/reference scoreboard + liveness assertions |
Start with a deliberately narrow support matrix, such as aligned INCR reads, one ID, and four outstanding transactions. Add one concurrency feature at a time and preserve evidence for every new ordering state.
The linked prerequisites distinguish ID streams from queue capacity: one ID can own four ordered outstanding contexts. If writes are later added, AW and W offers/handshakes need not occur in address-first temporal order; AXI4 associates non-interleaved W bursts with AW request order and has no WID. Buffer or backpressure early W data, and issue B only after the AW and final W handshakes. These ordering rules do not impose AW-before-W presentation.
Implement the running master in that order: first one burst context, then a four-entry request table and credit counter, then response retirement. Only after its ordering scoreboard and liveness properties pass should the design add multiple IDs or out-of-order completion.
The Protocols course owns protocol semantics and can evolve once. The RTL page focuses on implementation state, ownership, and the path from Lite to full AXI.