Every write ends with a two-bit B response and every read with a two-bit R response. AXI4-Lite permits OKAY, SLVERR and DECERR; EXOKAY is excluded. The minimal register bank implements only OKAY and SLVERR, while the default target below implements DECERR.
Code | Name | Meaning | Who sends it |
|---|---|---|---|
| OKAY | Normal success | Lite slaves and the interconnect |
| EXOKAY | Exclusive-access success | Full AXI only; never a Lite slave |
| SLVERR | Slave error: bad address or rejected access | Lite slave for unmapped or protected words |
| DECERR | Decode error: no target owns the address | Decode/default-target policy, including the Lite default slave below |
AXI4-Lite has no exclusive-request signals, so it cannot represent an exclusive request and must not return EXOKAY. DECERR is a legal Lite response; this fabric assigns it to the default target when no mapped target matches. SLVERR for an unimplemented word within the selected register bank is this bank's policy.
WSTRB has one bit per byte lane of WDATA: bit i enables byte i. A lane with its strobe high takes the new byte; a lane with its strobe low keeps the old byte.
WSTRB | Effect on a 32-bit word | Typical use |
|---|---|---|
| Full-word replace | Normal register write |
| One byte replaced | Byte-wide control or status bits |
| Low or high halfword replaced | 16-bit fields |
| Alternating bytes replaced | Packed byte arrays |
| Mapped writable word: nothing replaced, completes OKAY | No-op write; address errors still apply |
Worked example: the register holds 0x12345678 and a write arrives with data 0xAABBCCDD and strobes 4'b1010. Lanes 3 and 1 take new bytes (AA and CC) while lanes 2 and 0 keep old bytes (34 and 78), so the register becomes 0xAA34CC78.
Byte lane | 3 | 2 | 1 | 0 |
|---|---|---|---|---|
Old register | 12 | 34 | 56 | 78 |
WDATA | AA | BB | CC | DD |
WSTRB bit | 1 | 0 | 1 | 0 |
New register | AA | 34 | CC | 78 |
Read each column on its own: the strobe bit picks the WDATA byte (bold) when it is 1 and keeps the old byte when it is 0. The lanes never mix, so each byte is a separate 2-to-1 choice.
Zero strobes suppress byte updates, not address validation: a mapped writable word in this bank returns OKAY unchanged, an unmapped bank word returns SLVERR, and a request routed to the default target returns DECERR. The bank bench checks both mapped and unmapped zero-strobe writes. The default target has no WSTRB input because every paired write returns DECERR regardless of its strobes.
An interconnect routes each address to one slave, and every address it cannot route still needs an answer. A default slave accepts any paired write or any read and answers DECERR, so no master ever hangs on an unmapped access.
The listing below pairs AW and W exactly like a real slave, then responds without touching any register. Reads return zero data with DECERR.
// Default slave for unmapped addresses: accepts every request, answers DECERR.
module axilite_default_slave #(
parameter int AW = 8,
parameter int DW = 32
) (
input logic clk,
input logic rst_n,
input logic s_awvalid,
output logic s_awready,
input logic s_wvalid,
output logic s_wready,
output logic s_bvalid,
input logic s_bready,
output logic [1:0] s_bresp,
input logic s_arvalid,
output logic s_arready,
output logic s_rvalid,
input logic s_rready,
output logic [DW-1:0] s_rdata,
output logic [1:0] s_rresp
);
localparam [1:0] DECERR = 2'b11;
logic aw_seen, w_seen;
assign s_awready = !aw_seen && !s_bvalid;
assign s_wready = !w_seen && !s_bvalid;
assign s_arready = !s_rvalid;
assign s_bresp = DECERR;
assign s_rresp = DECERR;
assign s_rdata = '0;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
aw_seen <= 1'b0;
w_seen <= 1'b0;
s_bvalid <= 1'b0;
s_rvalid <= 1'b0;
end else begin
if (s_awvalid && s_awready) aw_seen <= 1'b1;
if (s_wvalid && s_wready) w_seen <= 1'b1;
if (aw_seen && w_seen && !s_bvalid) begin
s_bvalid <= 1'b1;
aw_seen <= 1'b0;
w_seen <= 1'b0;
end
if (s_bvalid && s_bready) s_bvalid <= 1'b0;
if (s_arvalid && s_arready) s_rvalid <= 1'b1;
if (s_rvalid && s_rready) s_rvalid <= 1'b0;
end
end
endmoduleNo: Lite lacks exclusive-request signals. EXOKAY is excluded; OKAY, SLVERR and DECERR are legal, with the implemented subset determined by the target's policy.
WSTRB = 4'b0000. What changes, and what response is returned?No bytes change. A mapped writable word in this bank returns OKAY, an unmapped bank word still returns SLVERR, and the default target returns DECERR. Zero strobes do not turn an invalid address into a successful access.
0x40 in a fabric with two slaves covering 0x00–0x07 and 0x10–0x17. Which block answers, and with what?The default slave, with DECERR on B. Neither real slave matches, so the fabric routes the request to the default path.
The default slave plus a testbench: a W-before-AW write and a read both answer DECERR, with stalls proving the responses hold.
module axilite_default_slave #(
parameter int AW = 8,
parameter int DW = 32
) (
input logic clk,
input logic rst_n,
input logic s_awvalid,
output logic s_awready,
input logic s_wvalid,
output logic s_wready,
output logic s_bvalid,
input logic s_bready,
output logic [1:0] s_bresp,
input logic s_arvalid,
output logic s_arready,
output logic s_rvalid,
input logic s_rready,
output logic [DW-1:0] s_rdata,
output logic [1:0] s_rresp
);
localparam [1:0] DECERR = 2'b11;
logic aw_seen, w_seen;
assign s_awready = !aw_seen && !s_bvalid;
assign s_wready = !w_seen && !s_bvalid;
assign s_arready = !s_rvalid;
assign s_bresp = DECERR;
assign s_rresp = DECERR;
assign s_rdata = '0;
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
aw_seen <= 1'b0;
w_seen <= 1'b0;
s_bvalid <= 1'b0;
s_rvalid <= 1'b0;
end else begin
if (s_awvalid && s_awready) aw_seen <= 1'b1;
if (s_wvalid && s_wready) w_seen <= 1'b1;
if (aw_seen && w_seen && !s_bvalid) begin
s_bvalid <= 1'b1;
aw_seen <= 1'b0;
w_seen <= 1'b0;
end
if (s_bvalid && s_bready) s_bvalid <= 1'b0;
if (s_arvalid && s_arready) s_rvalid <= 1'b1;
if (s_rvalid && s_rready) s_rvalid <= 1'b0;
end
end
endmodule