The question

The interviewer asks: four masters share one SRAM through an AXI fabric and the design hangs. Where do you look first, and how would you have prevented it?

This tests channel independence. Every AXI channel carries its own valid/ready, and a hang is almost always one side waiting on a channel the other side stopped serving.

Five channels, each with its own handshake

AXI separates address, data, and response into independently handshaken channels. Each moves on its own valid/ready pair. Transaction dependencies and shared capacity can nevertheless couple their progress: AW and W may arrive in either order, and a write response needs both accepted address and data.

Read the picture top to bottom: three write-side channels, then two read-side channels. Every arrow is its own valid/ready link.

• The two highlighted arrows are responses. A hang usually means one of them never comes, or comes and is never accepted.

• B depends on both AW and W. That cross-channel dependency is where most write hangs start.

• Nothing in the picture forces AW before W. A slave must accept them in either order.

The source holds address, control, and data stable until each handshake, exactly as in the previous lesson. Bursts end with the last-beat flag, and the response follows the last beat.

Three hangs and what the trace shows

Each hang below is a wait that never ends. On a waveform it looks the same every time: a VALID held high, or a response that never forms, for as long as you scroll.

1. Starved response

The master waits for R before accepting B, while shared slave capacity waits for B retirement before producing R.

Read each arrow as waits for. A deadlock is a closed loop in this graph; breaking any one arrow frees all three.

• Prevention: provide response capacity, or prove the dependency graph has no cycle.

• Drain R and B independently where possible, so a master never makes acceptance of one response wait for another.

2. Orphaned address

A write address is accepted but the write data never follows, so the response never forms.

Prevention: generate AW and W independently without waiting for READY; monitor missing data and define system-level fault recovery. A timeout cannot authorize an early B response.

3. Unmapped request

No slave is selected, so no response ever comes.

Prevention: decode every address to one slave or the default slave, as the next lessons show.

A legal rendezvous, and the forbidden circular wait

The one-write AXI-Lite slave below registers READY after observing both offers and a free write slot. This policy needs the master to hold both offers; it is not a universal throughput recommendation.

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// snippet: one-slot AXI-Lite control sketch; payload capture uses these handshakes.
// AWVALID and WVALID must remain asserted with stable payload until acceptance.
always_ff @(posedge ACLK) begin
  if (!ARESETn) begin
    AWREADY <= 0; WREADY <= 0; BVALID <= 0;
  end else if (AWREADY && WREADY) begin
    AWREADY <= 0; WREADY <= 0;
    // Both handshakes occur here; captured write completes successfully in this sketch.
    BVALID <= 1;
  end else if (BVALID) begin
    if (BREADY) BVALID <= 0;
  end else begin
    AWREADY <= AWVALID && WVALID;
    WREADY <= AWVALID && WVALID;
  end
end

Each slot is one ACLK cycle, sampled just after the rising edge. WREADY is identical to AWREADY in this sketch, so only AWREADY is drawn.

• Slot 1: AWVALID is high but WVALID is not, so the slave keeps READY low. The master keeps offering; it does not wait for AWREADY.

• Slots 2 to 3: WVALID joins in slot 2, the slave registers READY high for slot 3, and both handshakes happen at the edge that ends slot 3.

• Slots 4 to 5: BVALID holds for two slots because BREADY is low in slot 4. The response is accepted at the edge that ends slot 5.

• Slot 6: the slot is free again and READY can rise for the next write.

Forbidden circular wait: master waits for AWREADY before asserting WVALID; subordinate waits for WVALID before registering AWREADY. Starting with both low, neither can move. The master dependency violates AXI. A compliant master offers WVALID from pending data, as slot 2 shows, allowing the registered rendezvous to progress. In a real slave, BVALID additionally waits for actual write completion; capture payloads, strobes and error status and check stable B offers through acceptance.

Follow-ups

AWVALID is stuck high with no AWREADY. Check the slave clock and reset first, then the interconnect select and ready path, then the address map. A missing decode leaves no slave selected at all.

Common wrong answers

Backpressure means the bus is broken. Backpressure is flow control doing its job. Sustained backpressure means the buffering or arbitration is undersized, not that the protocol failed.

Posted writes need no response. The B response is still required for every address. Ignoring it leaks outstanding slots until the master stops.

“SLVERR always means retry” is unsafe. SLVERR means a slave could not complete an access successfully, for example because of an unsupported operation, internal timeout or unavailable resource. An interconnect that cannot decode an address returns DECERR. Retry policy depends on the device contract and whether repeating the access is safe and idempotent; an error alone is not permission to replay a write.

Notes: AXI4-Lite depth and timeouts

AXI4-Lite has no IDs but supports multiple outstanding transactions with ordered responses. A simple slave may deliberately limit each direction to one outstanding transaction using backpressure. Full AXI adds IDs to distinguish transaction streams and permit applicable cross-ID response reordering; concurrency alone does not require IDs.

Outstanding depth is an implementation limit, not a universal one-transaction AXI4-Lite rule. Lite can queue requests and respond in order without IDs; a one-entry slave is merely the smallest implementation.

If AW is accepted but W never comes, the slave must retain the outstanding transaction: AXI has no timeout-based cancellation handshake. In AXI4, BVALID requires an accepted address and all write data through the accepted WLAST beat; AXI4-Lite requires both accepted AW and W. A watchdog may report a separate system fault, stop admission and initiate coordinated isolation/reset, but must not fabricate an early B response or reuse the slot for an unrelated write. If recovery retains the link, define how late W data is drained and paired with the original address before returning an error. AW and W need not arrive together; neither VALID may wait for the other channel's READY.

Related topics

• AXI-Lite

• AXI-Stream