Combinational logic has no memory, yet its settling time sets the top clock speed.
3 lessons, about 14 min
assign statements contain state?Not by itself. A loop-free network of assign statements is purely combinational. A feedback loop is a different hazard. It forms a combinational loop, a gate loop with no clock, which tools flag. It is not an inferred latch, the storage the tool adds when an output is left unassigned.
The critical path: the slowest register-to-register route. Only shortening that path raises the clock rate.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Propagation Delay and Levels of Logic
Logic time = period - clk-to-Q - setup - uncertainty. Only the logic part is yours.
The gate delay in the worked budget (80 ps) is an example; use your own library and timing report.
Fan-out and wires slow a level down, so ten heavy levels can cost more than twenty light ones.
Rule of thumb: convert the clock period into a level budget before you write the block.
Zero-Delay Simulation vs Inertial Delay
Zero-delay RTL simulation checks function only. Timing comes from static timing analysis on the netlist.
An inertial delay swallows pulses shorter than the delay; a transport delay passes every pulse.
A 2:1 AND-OR mux can drop for a moment when only its select changes (a static-1 hazard).
Rule of thumb: never drive a clock gate, reset or output enable from raw combinational logic.
Critical-Path Mindset in RTL
Fix the worst negative-slack path first. The critical path moves after each fix.
A priority chain can become a parallel AND-OR select only if the requests are one-hot, so assert $onehot0.
Pipelining trades one cycle of latency for clock rate.
Rule of thumb: read the report first, then change the structure behind the worst path.
Mini project: a 32-bit leading-zero counter and normaliser
Interview: run a mock interview on this topic