Sequential logic stores state in flip-flops. A flop samples its data input at the active clock edge and holds it until the next edge.
5 lessons, about 25 min
The old value, the one present at the edge. The change arrives after the 0.05 ns hold window, so it leaves the sample alone and waits for the next edge. A change inside the hold window can take the wrong value or cause metastability. Ideal RTL simulation assumes zero delay unless a hold time is given.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Edge-Triggered State Elements
After edge n, Q holds the D value from just before that edge. Use a nonblocking assignment in always_ff.
D must be stable for setup before the edge and hold after it; a change inside the window can capture the wrong value or cause metastability.
A slower clock cures setup violations but not hold violations.
Rule of thumb: a flop passes data only at the edge; a latch passes it while its enable is active.
D Flip-Flop with Asynchronous Reset
Asynchronous reset clears Q at once, without waiting for a clock edge.
Release has recovery and removal times, like setup and hold; RTL simulation does not model them.
Never build a reset from combinational logic. Use one reset synchroniser per clock domain.
Rule of thumb: assert asynchronously, release synchronously.
Synchronous Reset and Register Enable
A synchronous reset is ordinary D logic; the sensitivity list holds the clock alone.
Reset is written first so it wins over enable and works even when the enable is low.
Reset only control state, valid bits and pointers. A synchronous reset needs a running clock.
Rule of thumb: reset comes first in the priority chain.
Clock Enable vs Gated Clock
A clock enable reloads Q every edge and the clock tree keeps toggling; a gated clock stops the edges.
Write plain enables; in an ASIC flow, synthesis inserts ICG cells on banks that share an enable. On FPGAs use clock enables.
Gating adds glitch, skew and scan-test constraints on the clock path.
Rule of thumb: never gate a clock with a bare AND; use a latch or an ICG cell.
A Hold Violation, Worked
Hold slack = t_cq,min + t_logic,min - (t_hold + skew). The clock period is not in it.
Positive skew (capture clock late) pushes the hold window later and eats hold slack; direct flop-to-flop links are the usual victims.
Recovery and removal are setup and hold for the release of an asynchronous reset; release it from a flop on the same clock.
Rule of thumb: if a hold fix involves the clock period, it is not a hold fix.
Mini project: a programmable timer with prescaler, compare and interrupt
Practice question: Synchronous D flip-flop with reset
Code lab: 8-bit D flip-flop
Practice question: Asynchronous-reset flip-flop: glitch-free reset and metastability
Practice question: Debugging metastability from asynchronous reset deassertion
Code lab: D flip-flop with asynchronous reset
Interview: run a mock interview on this topic