A pipeline flows when every stage works on a different, independent item each cycle. Three events break that flow, each with a standard response.
Event | What it means | Typical response |
|---|---|---|
Stall | A stage must wait (resource busy, data not ready) | Freeze earlier stages; hold their contents |
Bubble | A stage holds no useful work (an invalid slot) | Carry a valid bit so nothing downstream acts on it |
Flush | Work already in flight must be thrown away (wrong branch) | Clear the valid bits of the affected stages |
Read each column as one cycle and each row as one stage. An item moves down one row per cycle when nothing stops it.
Cycle 4, Fetch and Decode: B cannot leave Decode, so both stages hold their items. That is the stall.
Cycle 4, Execute: nothing arrived, so Execute holds an empty slot. That is the bubble.
Cycles 5 and 6: the flow resumes; every item is one cycle later than it would have been, and nothing was lost.
5 lessons, about 25 min
A stall holds work in place (the stage waits). A bubble is an empty slot travelling forward. Stalling the front of a pipe while the back keeps draining creates bubbles behind the stall.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Structural Hazard and Stall Logic
Fixed priority gives the port to the older stage and stalls the front.
A stalled stage holds both its data and its valid bit.
A global stall is a high-fanout net; local valid/ready handshakes scale better.
Pipeline Flush on Branch Resolve
On a taken branch, redirect the PC and clear the valid bits of all younger stages.
With the branch resolved in stage k, the sketch discards k - 1 instructions.
Flush must also stop side effects such as register writes and stores before commit.
Retiming-Friendly Coding Notes
Write data every cycle and qualify its use with valid, rather than gating the data write.
Adding N output ranks adds N cycles of latency; extend the valid delay and the consumers.
Retiming moves register names, so check equivalence at the outputs.
Data Hazards and Forwarding
Forward from every stage that holds a result not yet in the register file, youngest producer first.
A load in X has only its address; its consumer waits one cycle, then takes the data from W.
Check against an in-order reference model: hazard bugs give wrong values, not hangs.
Rule of thumb: if the producer is still in the pipe, the consumer reads the pipe, not the register file.
A Round-Robin Arbiter from a Priority Encoder
Mask the requests strictly above the last winner; if any survive take their first, else wrap to the first overall.
The double-width form searches {req, req} from bit last + 1 with dbl & ~(dbl - base) and folds the halves.
Load the pointer with the winner, and only when someone was granted.
Rule of thumb: the pointer moves on a grant and only on a grant; the mask starts one above the last winner.
Mini project: a programmable timer with prescaler, compare and interrupt
Practice question: Structural hazard detection unit
Code lab: Pipeline stall logic
Practice question: Branch misprediction flush logic
Practice question: Forwarding unit for pipeline data hazards
Code lab: Round-robin arbiter
Interview: run a mock interview on this topic