A pipeline runs at the speed of its slowest stage. Retiming slides registers across combinational gates to balance stage delays while keeping input/output behaviour unchanged.
3 lessons, about 14 min
No. Each path keeps the same number of registers (same latency). Registers move along the path; the total count can change only where paths fork or merge.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Retiming Mechanism
Moving the register backward across f puts it between g and f and splits the path.
The registers around every feedback loop must stay the same in number, or the function changes.
The retimed output is a combinational sum of registers, so clock-to-output delay and glitches can differ.
Retiming Decision Guide
Small imbalances suit the tool option; critical interfaces suit a manual rewrite.
Put the number of output ranks in a parameter, so adding a stage is a one-line change.
Re-run a protocol's testbench after retiming any block inside it.
Handshake-Aware Retiming
in_ready comes from the skid_v flag alone, so out_ready has no path to in_ready.
A skid buffer doubles the registers, keeps one item per cycle and can pause input for a cycle on recovery.
A one-register slice that just registers ready halves the rate or drops data.
Mini project: a programmable timer with prescaler, compare and interrupt
Practice question: Two-stage valid/ready pipeline and skid buffers
Code lab: Skid buffer
Interview: run a mock interview on this topic