The report below is built from the equations to show the layout. Real tools print the same information in their own format.
Startpoint: u_a/r_reg (rising edge-triggered flop clocked by clk)
Endpoint: u_b/s_reg (rising edge-triggered flop clocked by clk)
Path type: max (setup)
Data path
launch clock latency 0.62 (clock arrival at u_a/r_reg)
u_a/r_reg clk -> Q 0.35
U1 (NAND2) 0.22
U2 (XOR2) 0.31
U3 (AOI22) 0.28
U4 (NAND3, fanout 12) 0.40 <-- slowest cell
U5 (INV) 0.24
data arrival time 2.42
Capture path
clock period 2.00
capture clock latency 0.80 (clock arrival at u_b/s_reg)
setup time -0.12
clock uncertainty -0.15
data required time 2.53
slack (MET) 0.11Line | Meaning | Check |
|---|---|---|
launch clock latency 0.62 | Clock tree delay to the launch flop | Adds to the data arrival |
capture clock latency 0.80 | Clock tree delay to the capture flop | Skew = 0.80 − 0.62 = +0.18 ns, which helps setup |
logic cells | 0.22 + 0.31 + 0.28 + 0.40 + 0.24 | = 1.45 ns of combinational delay |
data arrival | 0.62 + 0.35 + 1.45 | = 2.42 |
data required | 2.00 + 0.80 − 0.12 − 0.15 | = 2.53 |
slack | 2.53 − 2.42 | = +0.11 ns |
Path type: min (hold)
launch clock latency 0.62
u_a/r_reg clk -> Q (min delay) 0.30
shortest logic path 0.10
data arrival time 1.02
capture clock latency 0.80
hold time 0.06
clock uncertainty (hold) 0.05
data required time 0.91
slack (MET) 0.11 (1.02 - 0.91)Both reports use one set of clock latencies and no on-chip-variation derates, so the shared part of the clock tree has the same delay for launch and capture and there is no pessimism to remove. A clock reconvergence pessimism removal (CRPR) line appears once early and late derates are applied; the next lesson adds them.
Required = 2.00 + 0.55 − 0.12 − 0.15 = 2.28. Slack = 2.28 − 2.42 = −0.14 ns. The path now fails because the skew is −0.07 instead of +0.18.
The setup and hold reports are constructed from the equations to show the layout. They are not output from a specific tool.