STA Mastery · All levels

Constraints & SDC Fundamentals

Clocks, generated clocks, uncertainty, I/O delay, false paths, multicycle paths, case analysis, and constraint quality audits.

Section goal

Clocks, generated clocks, uncertainty, I/O delay, false paths, multicycle paths, case analysis, and constraint quality audits.

How to study this section

Start with the topic hub to learn the contract.
Use mechanism and reports pages to connect rules to metrics.
Use debug and worked-example pages for interview and on-call practice.
Close with checklist and PPA impact before signing any change.

Topics

clock-definition-and-uncertainty/ — Clock Definition & Uncertainty
generated-clocks-and-dividers/ — Generated Clocks & Dividers
io-timing-and-boundary-contracts/ — I/O Timing & Boundary Contracts
exceptions-audit-policy/ — Exceptions & Audit Policy

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

diagram

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

clock report
uncertainty budget
IO delay coverage
exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

Diff SDC before ECO
Validate clocks on failing path
Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Practice this lesson

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