Timing analysis checks the design against the constraints you give it. Wrong constraints give confident wrong answers, so this section teaches each constraint family as a claim about the design: what it says, what evidence supports it, and how to audit it. Commands are shown as standard SDC and explained; none of the blocks claim a particular tool's output.
Lesson | After it you can... |
|---|---|
Define a clock and say what it implies. | |
Handle duty cycles and offsets. | |
Apply setup and hold uncertainty. | |
Set the right latency for the clock model. | |
Define a derived clock. | |
Decide when a generated clock is needed. | |
Constrain clock selection. | |
Audit clock reachability. | |
Derive boundary delays. | |
Budget a period between two blocks. | |
Use an external clock reference. | |
Find missing port constraints. | |
Justify and scope a false path. | |
Set setup and hold multipliers. | |
Bound a path by explicit delay. | |
Audit overbroad and stale exceptions. | |
Fix constants and remove arcs. | |
Apply design-rule limits. | |
Avoid unit and corner mix-ups. | |
Run the pre-timing checks. |
Suggested order: top to bottom. Before reading slack in any real project, run the clock audit, the I/O audit, the exception audit and the sanity checks from this section. The RTL view of the same topics is in Multi-Cycle and False Paths and the synthesis view in Synthesis constraints.
The clock audit (no unclocked pins), the I/O constraint audit, the exception audit, the design-rule violations and the constraint sanity checks. Each looks for a different class of silent error.