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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
    • Clock Definition & Uncertainty
    • Generated Clocks & Dividers
    • I/O Timing & Boundary Contracts
    • Exceptions & Audit Policy
      • False Paths
      • Multicycle Paths
      • Min and Max Delay Exceptions
      • Exception Audit
    • Environment and Design Rules
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Exceptions & Audit Policy
  1. Topics
  2. Static Timing Analysis
  3. Constraints & SDC Fundamentals
  4. Exceptions & Audit Policy
  5. Multicycle Paths

Part 2 · Constraints and SDC · All levels

Multicycle Paths

A multicycle path gives data N cycles to arrive; the setup multiplier moves the capture edge, and the hold multiplier must be set to keep hold at the right edge.

On this page

    Why it matters

    Some paths are designed to take more than one clock cycle: the data is held stable and captured only every N cycles. Telling STA lets it check against the real capture edge instead of a one-cycle requirement that the design deliberately does not meet. The command has a well-known trap: setting only the setup multiplier moves the hold check too.

    Setup and hold multipliers

    Diagram
    # not-run: SDC is not executable here
    set_multicycle_path 3 -setup -from [get_pins cfg_reg*/CK] -to [get_pins eng_reg*/D]
    set_multicycle_path 2 -hold  -from [get_pins cfg_reg*/CK] -to [get_pins eng_reg*/D]
    example.py
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    # Same clock, period T. Edges counted in cycles after the launch edge (launch = 0).
    def edges(setup_n, hold_n=0):
        setup_capture = setup_n              # data may take up to setup_n cycles
        hold_capture = (setup_n - 1) - hold_n   # default hold check is one cycle before the setup capture edge
        return setup_capture, hold_capture
    # default path
    assert edges(1) == (1, 0)
    # 3-cycle path with only the setup multiplier: hold is checked 2 cycles after launch (too late; wrong)
    assert edges(3) == (3, 2)
    # with the hold multiplier 2: hold is back at the launch edge
    assert edges(3, hold_n=2) == (3, 0)
    print("PASS: setup 3 + hold 2 gives capture edge 3, hold edge 0")

    A default path has its setup capture at one cycle and hold check at the launch edge (0). Setting -setup 3 alone moves the setup capture to 3 and drags the hold check to edge 2. That means new data must not arrive before about 2T after launch, which is usually false: the hold check becomes far too pessimistic and forces large delay padding. The fix is -hold 2, which pulls the hold check back to edge 0. The rule of thumb is hold multiplier = setup multiplier - 1.

    Reference clock

    The multipliers count cycles of a reference clock. With the same clock on both ends it does not matter. When launch and capture clocks differ, the option that selects the reference, -start (launch clock reference) or -end (capture clock reference), changes the result, so write it explicitly and check the report's launch and capture times.

    What the review looks for

    • Every multicycle path has a matching hold exception, and the report's capture and hold edges match the intended ones.

    • The design really holds the data stable for N cycles (an enable or a handshake), and an assertion or protocol check exists.

    • Multicycle paths are listed with their N and their evidence, and not extended "to make it pass".

    Common pitfall

    Applying a multicycle without a protocol that guarantees the data is stable and captured only every N cycles. The path may then fail in silicon whenever the data changes in the extra cycles: STA now allows it and nothing else checks it.

    Interview

    If asked about the hold side of a multicycle path, give the rule (same clock, equal periods; reference the capture clock with -end) and say why: the hold check moves with the setup capture edge unless you move it back.

    Check yourself A path is a 4-cycle path. What setup and hold multipliers do you set, and what hold edge results?

    -setup 4 and -hold 3; the setup capture is at edge 4 and the hold check returns to edge 0 (the launch edge), matching a normal hold requirement.

    Related topics

    • False Paths

    • Next: Min and Max Delay Exceptions

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    See also

    • Exception Audit