Most chips derive clocks from a few sources: dividers, multipliers (PLLs), gates and muxes. Each derived clock must be known to the analysis or its flops are unconstrained. This topic covers create_generated_clock, dividers and gates, clock muxes and case analysis, and the checks that prove clocks reach where they should.
Lesson | After it you can... |
|---|---|
Define a derived clock with the right source and relationship. | |
Tell when a generated clock is needed and when not. | |
Constrain clock selection correctly. | |
Prove every clock pin has the intended clock. |
Related RTL-side material: Clock Architecture and Clock Gating.
When a clock signal leaves a sequential cell's output (a divider or toggle flop) or is otherwise created by logic that STA does not propagate the source clock through. Combinational gates and buffers on the clock path do not need one.