Generated Clocks & Dividers

What this topic teaches

Generated Clocks & Dividers is about converting constraints and path rules into measurable slack. Generated clocks propagate from master clocks through dividers and muxes; incorrect -divide or -edges breaks downstream path grouping. The hard part is never the textbook inequality; it is proving, under the right corner/mode/view, which layer — constraint, view, or implementation — broke the contract.

The senior-engineer question

When generated clock reachability, divide-by mismatch, pulse width violations moves, can you identify the failing path group, the STA layer, the responsible owner, and the smallest experiment that proves the root cause?

STA CLOSURE FLOW — Generated Clocks & Dividers

constraints (SDC)
        |
        v
timing graph (cell + net delays)
        |
        v
MMMC scenarios (corner x mode x view)
        |
        v
variation + SI adjustments
        |
        v
slack (WNS/TNS) -> ECO -> regression

Debug rule: always state corner, mode, view, and database tag with slack.

Picture the timing closure flow

Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.

Generated clock propagation

MASTER CLK ~~~~~~~~~~~~~~~~~~~~~~~~
                |
           [divider / mux]
                |
GEN CLK   ~~~~~~|~~~~~~  (create_generated_clock)

Every downstream path must use the correct launch/capture clock.
Missing generated clock -> paths analyzed on wrong period.

Timing path sequence

TIMING PATH — Generated Clocks & Dividers

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: generated clock reachability, divide-by mismatch, pulse width violations

Who owns which layer

STA OWNERSHIP LAYERS — Generated Clocks & Dividers

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

Evidence to collect

• Primary metric: generated clock reachability, divide-by mismatch, pulse width violations.

• Primary artifact: report_clock -attributes, generated clock tree diagram, SDC generated_clock block.

• Owners to bring into review: STA owner, RTL owner, clock integration owner.

• Spec clause or requirement ID for every constraint claim.

• One failing report_timing excerpt and one reduced path that isolates the rule.

Ownership map

OWNERSHIP MAP — Generated Clocks & Dividers

artifact              owner
----------------      -----------------
timing report       STA owner
SDC/constraint      RTL owner
implementation      clock integration owner

Every WNS cluster needs a named owner before ECO.

Subpages in this topic

Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

• State corner, mode, and view with every slack number.

• Separate constraint bugs, view mismatches, and real path delays before ECO.

• Run setup and hold plus full MMMC after every change.

Common pitfalls

• Comparing runs with different SPEF or SDC tags.

• Broad false_path to hide violations.

• Setup-only ECO without hold regression.

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

• clock report

• uncertainty budget

• IO delay coverage

• exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

• Diff SDC before ECO

• Validate clocks on failing path

• Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

• State corner, mode, view, and database tag with every slack claim.

• Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

• Comparing STA runs with different SPEF or SDC tags.

• Broad false_path to green-wash violations.

• Setup-only ECO without hold check.