A divider flop's output drives clock pins, but STA does not propagate the master clock through the flop. create_generated_clock tells the tool where the new clock appears and how it relates to its master. With it, the downstream flops are clocked, the relationship between master and derived clocks is known, and the delay through the divider counts as clock latency.
# not-run: SDC is not executable here
create_generated_clock -name clk_div2 -source [get_ports clk] -divide_by 2 [get_pins div_reg/Q]
create_generated_clock -name clk_x2 -source [get_ports clk] -multiply_by 2 [get_pins pll_out]
create_generated_clock -name clk_div4 -source [get_ports clk] -edges {1 5 9} [get_pins div4_reg/Q]
create_generated_clock -name clk_inv -source [get_ports clk] -divide_by 1 -invert [get_pins inv_reg/Q]Option | Meaning |
|---|---|
-source | The master clock point the derived clock comes from (a pin or port where the master is defined or propagated) |
-divide_by N / -multiply_by N | Period of the derived clock is N times longer / N times shorter than the master |
-edges {a b c} | Rise at master edge a, fall at b, rise at c (edges counted from 1 at the first master rising edge) |
-invert | The derived clock is the inverse of the divided waveform |
-master_clock | Selects the master when several clocks reach the source pin |
# Generated clock waveform from master edges: -edges {1 3 5} on a 10 ns master (rise at 0, fall at 5)
master_period = 10.0
def master_edge(n): # edge 1 = rise at 0, 2 = fall at 5, 3 = rise at 10, ...
return (n - 1) * master_period / 2.0
rise, fall, rise2 = master_edge(1), master_edge(3), master_edge(5) # {1 3 5}: rise 0, fall 10, rise 20
period = rise2 - rise
assert (rise, fall, rise2) == (0.0, 10.0, 20.0) and period == 20.0
assert period == 2 * master_period # equal to -divide_by 2
print("PASS: -edges {1 3 5} gives a divide-by-2 clock, period", period, "ns")The edge list {1 3 5} picks the first, third and fifth master edges: rising at 0, falling at 10, rising at 20. The derived period is 20 ns, twice the master's, with a 50% duty cycle, identical to -divide_by 2. Use -edges when the duty cycle or phase is not a plain division.
Every divider, toggle flop or clock-generating cell has a generated clock; the clock list in the report shows each with its master and period.
The generated clock is defined on the output pin of the dividing cell, and its master points to a real clock source.
The delay through the divider shows up in the derived clock's latency under propagated clocks.
create_generated_clock -divide_by 4 produce from a 2 ns master?8 ns, four times the master period.