Beyond clocks and exceptions, a constraint file carries the conditions the design operates in: pins held at constants, arcs that must not be timed, the limits on transition and capacitance, and the units everything is read in. This topic covers each and ends with sanity checks that catch constraint-file errors early.
Lesson | After it you can... |
|---|---|
Choose between constants and disabled arcs. | |
Apply design-rule limits and read their violations. | |
Avoid unit and corner mix-ups. | |
Run the checks that find constraint errors before timing. |
Case analysis fixes a pin to a constant and lets the tool propagate it (removing the arcs that constant disables). A false path removes the check between named points without changing logic values.