A library characterises cells only up to some maximum input transition and output load. Beyond them delay numbers are extrapolated and unreliable, and the physical behaviour (noise, power) degrades. Design-rule constraints turn those limits into checks so the timing numbers can be trusted. Two limits look alike: the library's own max_transition is the characterised range, beyond which the tables are extrapolated; a project set_max_transition is a design limit, often tighter, and breaking it breaks the project's slew budget rather than the library tables.
# not-run: SDC is not executable here
set_max_transition 0.30 [current_design] ;# no net may have a slew above 0.30 ns
set_max_capacitance 0.080 [get_ports data_out] ;# limit on a driver's load
set_max_fanout 20 [current_design] ;# limit on fanout (units: loads)Rule | What exceeding it means | Typical fix |
|---|---|---|
Max transition | Slow edge: larger delay, noise sensitivity, short-circuit power | Buffer the net or upsize the driver |
Max capacitance | Driver loaded beyond its characterised range | Buffer, split fanout, upsize |
Max fanout | Too many loads on one driver | Buffer tree |
Min pulse width / period | Covered in the advanced checks section | n/a here |
# Transition check on nets: slew limit 0.30 ns
nets = {"n1": 0.18, "n2": 0.34, "n3": 0.30, "n4": 0.52}
limit = 0.30
viol = {n: round(s - limit, 2) for n, s in nets.items() if s > limit}
assert viol == {"n2": 0.04, "n4": 0.22}
assert "n3" not in viol # equal to the limit is not a violation
worst = max(viol.values())
assert worst == 0.22
print("PASS: transition violations", viol)Two of four nets exceed the 0.30 ns limit, by 0.04 and 0.22 ns; the net exactly at 0.30 ns passes. A design-rule violation is not a timing violation: it says the net breaks the project's slew budget there, so a clean slack on that path is not a guarantee.
Design-rule violations are zero (or individually signed off) before timing is trusted.
Limits come from the library and the project's rules, not from tuning to pass.
Rule violations are fixed by structural change (buffering, sizing), not by raising the limit.
No. The net breaks the project's 0.30 ns slew limit: slow edges inflate delay, noise sensitivity and short-circuit power, so the positive slack cannot be trusted until the net is fixed by buffering or upsizing, not by raising the limit.