STA Mastery · All levels

Clock Definition & Uncertainty

Constraints & SDC Fundamentals: SDC clocks define launch and capture time bases; uncertainty and skew model timing margin consumed before data-path delay is evaluated.

What this topic teaches

Clock Definition & Uncertainty is about converting constraints and path rules into measurable slack. SDC clocks define launch and capture time bases; uncertainty and skew model timing margin consumed before data-path delay is evaluated. The hard part is never the textbook inequality; it is proving, under the right corner/mode/view, which layer — constraint, view, or implementation — broke the contract.

The senior-engineer question

When WNS/TNS on clocked paths, clock skew reports, uncertainty budget moves, can you identify the failing path group, the STA layer, the responsible owner, and the smallest experiment that proves the root cause?

diagram

STA CLOSURE FLOW — Clock Definition & Uncertainty

constraints (SDC)
        |
        v
timing graph (cell + net delays)
        |
        v
MMMC scenarios (corner x mode x view)
        |
        v
variation + SI adjustments
        |
        v
slack (WNS/TNS) -> ECO -> regression

Debug rule: always state corner, mode, view, and database tag with slack.

Picture the timing closure flow

Start every study session by drawing the behavior before reading signals. The diagrams below are the mental models to reproduce on a whiteboard.

Launch vs capture clock domains

diagram

SETUP CHECK (simplified)

launch clock edge ----> data propagates through logic ----> arrives at capture FF
                                                              |
capture clock edge -----------------------------------------> required time
                                                              |
slack = required_time - arrival_time  (setup)

Hold is the reverse inequality: data must stay stable after capture edge.

Uncertainty budget stack

diagram

CLOCK UNCERTAINTY BUDGET

period
  |-- clock skew (CTS)
  |-- jitter (source + PLL)
  |-- uncertainty (SDC margin)
  |-- useful skew (if any)
  = effective capture window for data

If uncertainty is too small -> false optimism.
If too large -> wasted timing margin.

Timing path sequence

diagram

TIMING PATH — Clock Definition & Uncertainty

launch FF --logic stages--> capture FF
     |                           |
  launch clock                capture clock
     |                           |
  required: arrival < capture_edge - setup
  metric: WNS/TNS on clocked paths, clock skew reports, uncertainty budget

Who owns which layer

diagram

STA OWNERSHIP LAYERS — Clock Definition & Uncertainty

layer              owns                         failure mode
----------------   --------------------------   ---------------------
constraints        clocks, IO, exceptions       false violations
implementation     cells, nets, placement       real path delay
extraction         SPEF/RC corners              view mismatch
signoff policy     derate, MMMC matrix          margin disputes
closure           ECO order, regression        fix breaks other corner

Evidence to collect

Primary metric: WNS/TNS on clocked paths, clock skew reports, uncertainty budget.
Primary artifact: report_clock, clock tree report, SDC clock block, skew histogram.
Owners to bring into review: STA owner, synthesis owner, CTS owner.
Spec clause or requirement ID for every constraint claim.
One failing report_timing excerpt and one reduced path that isolates the rule.

Ownership map

diagram

OWNERSHIP MAP — Clock Definition & Uncertainty

artifact              owner
----------------      -----------------
timing report       STA owner
SDC/constraint      synthesis owner
implementation      CTS owner

Every WNS cluster needs a named owner before ECO.

Subpages in this topic

Each topic is taught across mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory, design space, expanded case study, walkthrough, comparison matrix, software view, and silicon PPA impact.

Key takeaways

State corner, mode, and view with every slack number.
Separate constraint bugs, view mismatches, and real path delays before ECO.
Run setup and hold plus full MMMC after every change.

Common pitfalls

Comparing runs with different SPEF or SDC tags.
Broad false_path to hide violations.
Setup-only ECO without hold regression.

STA deep dive

SDC quality determines whether STA measures reality or fiction.

Concept diagram

diagram

SDC FLOW

RTL clocks -> create_clock / generated_clock
board      -> set_input/output_delay
exceptions -> false_path / multicycle (audited)
analysis   -> report_timing

Metric graph

diagram

CONSTRAINT QUALITY

audited exceptions  ████████████████  good
stale IO delays     ██████            risk
missing gen clock   ████              high escape

Reports and artifacts

clock report
uncertainty budget
IO delay coverage
exception audit log

Mini case study

1000 new failing paths overnight: SDC merge dropped a generated_clock on divider output. No PD change needed.

Debug branches

Diff SDC before ECO
Validate clocks on failing path
Audit false paths quarterly

Senior review question

Ask: what corner/mode/view proves this topic is closed or failing?

Key takeaways

State corner, mode, view, and database tag with every slack claim.
Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

Comparing STA runs with different SPEF or SDC tags.
Broad false_path to green-wash violations.
Setup-only ECO without hold check.

Practice this lesson