Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
    • Clock Definition & Uncertainty
      • create_clock Rules
      • Waveform and Edge Cases
      • Uncertainty and Jitter
      • Source Versus Network Latency
    • Generated Clocks & Dividers
    • I/O Timing & Boundary Contracts
    • Exceptions & Audit Policy
    • Environment and Design Rules
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
Loading lesson

‹Clock Definition & Uncertainty
  1. Topics
  2. Static Timing Analysis
  3. Constraints & SDC Fundamentals
  4. Clock Definition & Uncertainty
  5. Uncertainty and Jitter

Part 2 · Constraints and SDC · All levels

Uncertainty and Jitter

set_clock_uncertainty subtracts margin from setup and adds it to hold; it covers jitter and skew estimation error.

On this page

    Why it matters

    Real clocks are not perfect: their edges move cycle to cycle (jitter), and before the clock tree is final the skew between flops is only estimated. Clock uncertainty is the margin that covers these. Too little hides real failures; too much wastes performance. Its value should be a decision with a documented reason.

    The command

    Diagram
    # not-run: SDC is not executable here
    set_clock_uncertainty -setup 0.12 [get_clocks sys_clk]
    set_clock_uncertainty -hold  0.05 [get_clocks sys_clk]
    set_clock_uncertainty -setup 0.20 -from [get_clocks clk_a] -to [get_clocks clk_b]   ;# inter-clock

    Source of uncertainty

    Affects

    Typical treatment

    PLL and clock source jitter

    Setup (period variation), and a smaller amount of hold

    A budgeted value per clock from the clock design

    Skew not yet known (pre-CTS)

    Setup and hold

    A larger value, reduced after clock tree synthesis

    Duty-cycle distortion

    Half-cycle paths

    Included for half-cycle checks

    Project margin

    Both

    A visible, owned number, never hidden in a derate

    example.py
    1
    2
    3
    4
    5
    6
    7
    8
    # Uncertainty effect on one setup path (ns, illustrative)
    T, S, arrival, C = 2.0, 0.10, 1.70, 0.35
    def slack(U): return (T + C - S - U) - arrival
    s_small, s_large = slack(0.05), slack(0.15)
    assert abs(s_small - 0.50) < 1e-9 and abs(s_large - 0.40) < 1e-9
    # every 0.1 ns of setup uncertainty removes 0.1 ns of slack, on every path of that clock
    assert abs((s_small - s_large) - 0.10) < 1e-9
    print("PASS: +0.10 ns uncertainty costs 0.10 ns slack on every path")

    Uncertainty acts uniformly on every path of the clock, so a small change moves WNS, TNS and the failing count together. That makes it a blunt tool and a common source of arguments in closure reviews.

    What the review looks for

    • A documented rationale: clock-source jitter figure, skew estimate, and project margin listed separately.

    • Pre-CTS uncertainty is reduced after the clock tree is built; leaving it large wastes closure effort.

    • Setup and hold uncertainties differ when they should: jitter mostly matters for setup.

    Common pitfall

    Using uncertainty to hide pessimism or a design problem. Raising it to "be safe" costs real performance; lowering it to pass a path removes real margin. Change it only with evidence.

    Interview

    Say what uncertainty models (jitter, skew estimation error, margin) and its sign (it reduces setup time and increases hold requirement).

    Check yourself Why is setup uncertainty usually larger than hold uncertainty?

    Jitter changes the period seen by a path, which directly eats setup time, while hold is a same-edge check where jitter largely cancels. Hold uncertainty mostly covers skew estimation error.

    Related topics

    • Waveform and Edge Cases

    • Next: Source Versus Network Latency

    • RTL: Skew and Uncertainty

    Previous

    24 / 183

    Next: Source Versus Network Latency

    Up next

    Up nextSource Versus Network Latency

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • create_clock Rules