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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
    • Clock Definition & Uncertainty
    • Generated Clocks & Dividers
      • create_generated_clock
      • Dividers and Gated Clocks
      • Clock Muxes and Case Analysis
      • Verifying Clock Propagation
    • I/O Timing & Boundary Contracts
    • Exceptions & Audit Policy
    • Environment and Design Rules
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Generated Clocks & Dividers
  1. Topics
  2. Static Timing Analysis
  3. Constraints & SDC Fundamentals
  4. Generated Clocks & Dividers
  5. Verifying Clock Propagation

Part 2 · Constraints and SDC · All levels

Verifying Clock Propagation

Constraint checks that prove every clock pin has exactly the clocks you intended, and flag the ones that do not.

On this page

    Why it matters

    A clock constraint can look right and still fail to reach the flops it was meant for. The way to find out is to ask the tool, and to look at the answers: which clocks reach which pins, which sequential pins have none, and which have more than one.

    The checks

    Check

    Finding

    Typical cause

    Sequential pins with no clock

    The pin's endpoint is unconstrained

    Missing generated clock; broken case analysis; unconnected gate

    Pins with multiple clocks

    Mixed or multiplexed clocks; a possible constraint error

    Missing mux handling; a clock reconvergent path

    Clocks with no sinks

    A defined clock that reaches no sequential pin

    Wrong source point; typo in a port name

    Generated clocks without a master

    Master not found or misdefined

    Source pin wrong

    Combinational loops on clock nets

    Unstable timing

    A design problem

    example.py
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    # Audit counts for a clock report (illustrative numbers): every flop must have exactly one clock.
    flops = 12000
    by_clock = {"sys_clk": 9200, "div2": 2400, "scan_clk": 300}
    no_clock = flops - sum(by_clock.values())
    assert no_clock == 100
    multi = 0
    status = "clean" if no_clock == 0 and multi == 0 else "needs work"
    assert status == "needs work"
    print("PASS: audit finds", no_clock, "flops with no clock out of", flops)

    The counts add up to 11,900 clocked flops out of 12,000: 100 flops have no clock. A clean run is zero unclocked pins and zero multi-clock pins (or explained ones). This count is the first number to look at after loading constraints, before any slack.

    What the review looks for

    • Clock reports are part of every constraint review, with the unclocked and multi-clock counts at or explained to zero.

    • Each defined clock has the expected number of sinks; large deviations are investigated.

    • Re-running the checks after any change to clocks, dividers or muxes is a gate, not an option.

    Common pitfall

    Trusting the slack report without checking the clock report. A design with 100 unclocked flops can show excellent slack because those paths are not timed at all. Always read the clock audit first.

    Interview

    If asked what you check first when you load constraints, say the clock list and the unclocked sequential pin count.

    Check yourself After adding a new divider, WNS looks better than before. What do you check?

    Whether the flops after the divider are clocked. A missing generated clock removes them from timing, so slack can improve because paths disappeared. Check the unclocked pin count.

    Related topics

    • Clock Muxes and Case Analysis

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    See also

    • create_generated_clock
    • Dividers and Gated Clocks