With a clock mux, both input clocks propagate to the flops after it. Without guidance the tool times data paths launched by one clock and captured by the other, even if the mux can never select both. That produces meaningless violations or hides real ones. You constrain the mux so the timed combinations match reality.
# not-run: SDC is not executable here
set_case_analysis 0 [get_pins clk_mux/S] ;# select fixed: only one clock propagates
set_clock_groups -logically_exclusive -group {clk_a} -group {clk_b} ;# both exist, never active together
set_clock_groups -asynchronous -group {clk_a} -group {clk_b} ;# unrelated clocks, no timing between themTool | Meaning | Use when |
|---|---|---|
set_case_analysis | Forces a pin to a constant for the analysis; the other mux input stops propagating | Analysing one mode at a time (see MMMC) |
set_clock_groups -logically_exclusive | The clocks cannot be active at the same time in the same mode; no checks between them | A mux whose select is dynamic, both clocks exist |
set_clock_groups -physically_exclusive | The clocks are on the same net and cannot coexist physically | Alternate clocks on one pin |
set_clock_groups -asynchronous | Clocks are unrelated; no checks between groups | Truly asynchronous domains (crossings handled by CDC methods) |
# Pair counting: how many clock-to-clock path groups does the tool time with 3 clocks?
clocks = ["a", "b", "c"]
ordered_pairs = [(x, y) for x in clocks for y in clocks] # includes same-clock pairs
assert len(ordered_pairs) == 9
exclusive_ab = [p for p in ordered_pairs if set(p) != {"a", "b"} or p[0] == p[1]]
assert len(exclusive_ab) == 7 # a<->b cross pairs removed (2 pairs)
print("PASS: marking a and b exclusive removes 2 of 9 clock pairs from timing")With three clocks there are nine launch-to-capture clock pairs. Declaring a and b exclusive removes the two cross pairs. The review question is always the reverse: is anything real hiding in the removed pairs? A cross-pair that does carry real data is a missed check.
Each exclusive or asynchronous group has a written reason (what proves the clocks never overlap or are truly unrelated).
Asynchronous groups are matched by a CDC signoff: removing timing checks between clocks is only safe if the crossings are verified separately.
Case analysis constants match the mode being analysed, and the modes are all analysed (MMMC).
Only if they never run at the same time through the mux. If both are active in the chip at once (for different blocks), they are not exclusive, and you need correct relationships (related or asynchronous) instead.