Deciding whether a structure needs a generated clock is the most common clock-constraint question. The rule is mechanical once you see it, and applying it prevents both silent unconstrained flops and redundant definitions.
Structure | Generated clock needed? | Why |
|---|---|---|
Divide-by-2 toggle flop driving flop clocks | Yes | The clock does not propagate through the flop's CK to Q arc |
AND gate with an enable (clock gate) feeding flop clocks | No | The clock propagates through the combinational gate; the enable gets a gating check |
Integrated clock-gating cell | No | Treated like a gate with a built-in latch; gating check on the enable |
Inverter or buffer chain on the clock | No | Clock network |
Clock mux between two defined clocks | No | Both clocks propagate; constrain selection (next lesson) |
PLL output with a different frequency | Yes (or define the clock at the PLL output pin) | The multiplied clock is a new waveform |
# Latency of a divided clock domain: path to the divider flop's CK + CK->Q + tree below it.
to_div_ck = 0.40 # ns master tree to the divider flop
ck_to_q = 0.45 # divider flop CK->Q
tree_below = 0.30 # buffers to the leaf flops
latency_div = to_div_ck + ck_to_q + tree_below
latency_master_leaf = 0.40 + 0.35
assert abs(latency_div - 1.15) < 1e-9
skew_between_domains = latency_div - latency_master_leaf
assert abs(skew_between_domains - 0.40) < 1e-9
print("PASS: divided domain latency", latency_div, "ns; skew vs master domain", skew_between_domains)The divided domain's flops see 1.15 ns of latency against 0.75 ns for the master leaf flops, a 0.40 ns skew. Because the divided clock is related to the master (same source), paths between the domains are timed with that skew unless the tree is balanced through the divider. Unbalanced dividers are a classic hold-risk source.
No flop is left without a clock after a divider is added; the unclocked-pin count stays at zero.
Gating checks exist for every clock gate enable (the advanced checks section covers them).
Skew between master and divided domains is understood: balanced by design or deliberately handled with hold fixing.
No. The master clock propagates through the clock-gating cell like through any combinational clock element. Add a gating check on its enable; no generated clock is needed.