Inside a block the load on each net comes from the netlist: the pin capacitances of the sinks plus the wire. At the block boundary the tool does not know what is outside, so you must tell it: how strongly the signal that enters the block is driven, and how much load an output port must drive. Wrong boundary models give wrong delay and slew on the first and last cells of every path.
pin_caps_fF = [2.0, 2.0, 2.5] # three sink pins
wire_fF = 5.0
load = sum(pin_caps_fF) + wire_fF
assert abs(load - 11.5) < 1e-9
print("PASS: load on the net =", load, "fF")The driver sees 11.5 fF: 6.5 fF of pins plus 5 fF of wire. A cell with the table from the previous lessons would be interpolated at that load. Adding one more fanout raises both the pin sum and typically the wire, so the delay climbs. This is why high-fanout nets are buffered.
# not-run: SDC is not executable here
set_driving_cell -lib_cell BUF_X2 [get_ports data_in] ;# models the cell driving this input
set_load 0.050 [get_ports data_out] ;# capacitive load on an output, in library capacitance units
set_input_transition 0.15 [get_ports mode] ;# alternative: fix the input slew directly, in library time unitsConstraint | What it means | What it does NOT mean |
|---|---|---|
set_driving_cell | Input is driven by a given cell, so its slew depends on load | Does not set the signal arrival time, which still comes from set_input_delay; it models the driver's drive strength (the load-dependent delay and the slew at the port) |
set_load | Adds capacitance to an output port or net | Does not model the delay of the outside logic |
set_input_transition | Fixes the slew at an input regardless of load | Does not model how slew would change with the load |
Every input port has a driving cell or transition and every output port a load; missing values default to ideal (zero) models, which are optimistic.
Boundary values are consistent with how the block will actually be used at the next level up.
Fanout-heavy nets are checked against the library's maximum fanout, capacitance and transition limits.
An ideal driver with zero transition at the port, so the first gate's delay is smaller than in real use. The port's slew should be modelled with a driving cell or an input transition.