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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
    • What STA Checks
    • Setup and Hold Checks
    • Clocks in Timing Analysis
    • Delay Models
      • Cell Delay Tables and Slew
      • Net Delay and Parasitics
      • Loads and Driving Cells
      • How Delay Calculation Flows
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Delay Models
  1. Topics
  2. Static Timing Analysis
  3. Timing Paths and Checks
  4. Delay Models
  5. Net Delay and Parasitics

Part 1 · Timing Paths and Checks · All levels

Net Delay and Parasitics

Wire delay comes from the resistance and capacitance of the route; the Elmore delay is the standard first-order estimate.

On this page

    Why it matters

    As technologies shrink, wire delay becomes a large share of path delay. Timing analysis models a net as an RC network extracted from the layout (or estimated before routing). The Elmore delay gives a quick first-order value that is good enough to judge whether a long wire is a problem and to check the order of magnitude of what the tool reports.

    The Elmore delay

    For an RC ladder driven by an ideal source, the Elmore delay to a node is the sum, over every resistor on the path from the driver to that node, of the resistance times the total capacitance downstream of that resistor. For two segments R1 with C1 at its far end, then R2 with C2:

    Diagram
    delay(node 2) = R1 x (C1 + C2) + R2 x C2
    example.py
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    R1, C1 = 100.0, 10e-15     # ohms, farads
    R2, C2 = 200.0, 20e-15
    elmore = R1 * (C1 + C2) + R2 * C2
    assert abs(elmore - 7.0e-12) < 1e-18          # 3 ps + 4 ps
    assert abs(R1 * (C1 + C2) - 3.0e-12) < 1e-18
    print("PASS: Elmore delay at the far node =", round(elmore * 1e12, 1), "ps")

    The first resistor sees all the capacitance beyond it (30 fF), contributing 100 x 30 fF = 3 ps; the second sees only its own 20 fF, contributing 200 x 20 fF = 4 ps; the total is 7 ps. Doubling the length of a uniform wire roughly quadruples its delay because both R and C double, which is why long wires are buffered. The Elmore value is an estimate (the first moment of the impulse response), not the 50% crossing: treat it as an upper-bound style estimate, since the 50% point is about 0.69 times it for a single pole.

    Pre-route and post-route

    Stage

    Parasitics source

    Accuracy

    Synthesis and early planning

    Wire-load or placement-based estimates

    Rough; used for direction

    After placement

    Estimated routes from placement

    Better; still optimistic or pessimistic by region

    After routing

    Extracted RC from real geometry (in corners)

    Signoff accuracy

    What the review looks for

    • The parasitic corner (typical, worst-RC, best-RC) is part of the view definition and matches the library corner.

    • Nets with unusually large RC delay are listed and buffered or re-routed; a long wire with a weak driver is a classic violation.

    • Correlation between the implementation and signoff extraction is checked; a systematic difference is a margin problem.

    Common pitfall

    Ignoring resistance on lower metal layers. At advanced nodes the thin lower layers are very resistive; a short route on the wrong layer can cost more delay than a long route on a thick upper layer. Layer assignment is part of timing closure.

    Interview

    If asked why wires matter more now, say that gate delay scales down with each node but wire RC per length does not, so the wire share of the path grows.

    Check yourself A uniform wire has delay 5 ps. Roughly what is the delay of the same wire twice as long, unbuffered?

    About 20 ps. Both its total resistance and capacitance double, so the RC product (and the Elmore delay) quadruples.

    Related topics

    • Cell Delay Tables and Slew

    • Next: Loads and Driving Cells

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    See also

    • How Delay Calculation Flows