As technologies shrink, wire delay becomes a large share of path delay. Timing analysis models a net as an RC network extracted from the layout (or estimated before routing). The Elmore delay gives a quick first-order value that is good enough to judge whether a long wire is a problem and to check the order of magnitude of what the tool reports.
For an RC ladder driven by an ideal source, the Elmore delay to a node is the sum, over every resistor on the path from the driver to that node, of the resistance times the total capacitance downstream of that resistor. For two segments R1 with C1 at its far end, then R2 with C2:
delay(node 2) = R1 x (C1 + C2) + R2 x C2R1, C1 = 100.0, 10e-15 # ohms, farads
R2, C2 = 200.0, 20e-15
elmore = R1 * (C1 + C2) + R2 * C2
assert abs(elmore - 7.0e-12) < 1e-18 # 3 ps + 4 ps
assert abs(R1 * (C1 + C2) - 3.0e-12) < 1e-18
print("PASS: Elmore delay at the far node =", round(elmore * 1e12, 1), "ps")The first resistor sees all the capacitance beyond it (30 fF), contributing 100 x 30 fF = 3 ps; the second sees only its own 20 fF, contributing 200 x 20 fF = 4 ps; the total is 7 ps. Doubling the length of a uniform wire roughly quadruples its delay because both R and C double, which is why long wires are buffered. The Elmore value is an estimate (the first moment of the impulse response), not the 50% crossing: treat it as an upper-bound style estimate, since the 50% point is about 0.69 times it for a single pole.
Stage | Parasitics source | Accuracy |
|---|---|---|
Synthesis and early planning | Wire-load or placement-based estimates | Rough; used for direction |
After placement | Estimated routes from placement | Better; still optimistic or pessimistic by region |
After routing | Extracted RC from real geometry (in corners) | Signoff accuracy |
The parasitic corner (typical, worst-RC, best-RC) is part of the view definition and matches the library corner.
Nets with unusually large RC delay are listed and buffered or re-routed; a long wire with a weak driver is a classic violation.
Correlation between the implementation and signoff extraction is checked; a systematic difference is a margin problem.
About 20 ps. Both its total resistance and capacitance double, so the RC product (and the Elmore delay) quadruples.