Why it matters

The traditional intuition is that heat slows silicon. In many modern technologies, at low supply voltage the opposite holds: delay is larger at low temperature. The effect depends on the technology, the voltage and the cell type, so libraries show it rather than a rule predicting it. Corners must include both temperature extremes for the low-voltage conditions.

Illustrative data

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# Relative delay of a reference path (typical process); illustrative values only.
delay = {
    (0.72, "hot"): 1.00, (0.72, "cold"): 1.12,     # low voltage: cold is slower
    (0.88, "hot"): 0.82, (0.88, "cold"): 0.74,     # high voltage: hot is slower
}
def slowest(v):
    return max(("hot", "cold"), key=lambda t: delay[(v, t)])
def fastest(v):
    return min(("hot", "cold"), key=lambda t: delay[(v, t)])
assert (slowest(0.72), slowest(0.88)) == ("cold", "hot")
assert (fastest(0.72), fastest(0.88)) == ("hot", "cold")
period, setup, path = 1.00, 0.06, 0.80
slack_cold = period - setup - path * delay[(0.72, "cold")]
slack_hot = period - setup - path * delay[(0.72, "hot")]
assert round(slack_cold, 3) == 0.044 and round(slack_hot, 3) == 0.140
print("PASS: low-V slowest", slowest(0.72), "; high-V slowest", slowest(0.88), "; setup slack cold", round(slack_cold, 3), "hot", round(slack_hot, 3))

At 0.72 V the cold condition is the slowest and the hot one the fastest; at 0.88 V it is the other way round. A 0.80 ns path has 0.044 ns of setup slack when cold and 0.140 ns when hot at 0.72 V: checking only the hot slow corner would overstate the margin by almost 0.1 ns. The same reversal applies to hold: at low voltage the fastest condition is hot.

Which corners that implies

Its relative delays are normalised to the typical-process hot condition at 0.72 V (= 1.00), a different normalisation from the operating-conditions lesson, where typical hot 0.80 V = 1.00.

What the review looks for

• Both temperature extremes appear in the low-voltage scenarios for setup and hold.

• The corner list states, from library data, which temperature is worst at each voltage.

• A new voltage domain triggers the question again: do not copy the corners of another domain.

Related topics

• RC Corner Mapping

• Why Corners Exist