Why it matters

Cell delay and setup time come from timing libraries. A chip uses several: standard cells, memories, IO cells and hard macros, each characterised separately. A scenario must load the right library from each family, each at the scenario's process and temperature, and at the voltage of its own supply domain. A single wrong file produces a plausible but wrong report.

The mapping

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corner = "ss_0p72v_125c"
expected = {
    "stdcell_hvt": corner,
    "stdcell_lvt": corner,
    "sram_1024x32": corner,
    "io_1p8": "ss_1p62v_125c",     # IO supply differs by design: same process and temperature, its own voltage
    "pll": corner,
}
loaded = {
    "stdcell_hvt": "ss_0p72v_125c",
    "stdcell_lvt": "ss_0p72v_125c",
    "sram_1024x32": "ss_0p72v_125c",
    "io_1p8": "ss_1p62v_125c",
    "pll": "tt_0p80v_25c",          # only a typical model was loaded
}
mismatch = sorted(k for k in expected if expected[k] != loaded[k])
assert mismatch == ["pll"]
print("PASS: mismatched libraries:", mismatch)

Four of five libraries match their expected corners; the PLL model is a typical-corner file inside a slow-corner scenario. Paths through or into the PLL are then timed with the wrong data. A check of this kind, run automatically over the loaded libraries, catches the error before anyone reads a slack.

What the review looks for

• A table per scenario of every loaded library, with its characterised corner.

• Any family with no library at the scenario's process and temperature, and at the voltage of its own supply domain, is listed with the margin used instead.

• Library versions are recorded: a refreshed library changes the numbers and must be a deliberate update.

Related topics

• Next: Operating Conditions