Libraries are characterised at discrete points. The supply seen by cells in the chip is not exactly the characterised one: it sags under load. Understanding how steeply delay depends on voltage shows how much a small droop costs in nanoseconds, and why the cost is largest at low-voltage corners.
# Relative delay of a reference path at three characterised voltages (typical process, hot).
points = {0.72: 1.30, 0.80: 1.00, 0.88: 0.82}
slope_low = (points[0.72] - points[0.80]) / (0.80 - 0.72) # delay change per volt, low segment
slope_high = (points[0.80] - points[0.88]) / (0.88 - 0.80)
assert abs(slope_low - 3.75) < 1e-9 and abs(slope_high - 2.25) < 1e-9
assert slope_low > slope_high
# 30 mV of droop at the low corner, applied to a path that takes 0.90 ns there (linear estimate)
droop = 0.030
delta = 0.90 * droop * slope_low / points[0.72]
assert round(delta, 3) == 0.078
print("PASS: slope low", slope_low, "high", slope_high, "; 30 mV droop adds about", round(delta, 3), "ns to a 0.90 ns path")Between 0.72 V and 0.80 V relative delay changes by 3.75 per volt, between 0.80 V and 0.88 V by only 2.25 per volt in absolute terms. Relative to each path's own delay that is 3.75 / 1.30, about 2.9 per volt at 0.72 V, against 2.25 / 0.82, about 2.7 per volt at 0.88 V: almost the same fractionally. A droop costs more nanoseconds at low voltage mostly because the path is longer in ns there. A 30 mV droop on a 0.90 ns path at 0.72 V is therefore worth roughly 0.078 ns, about 8.7% of the path as a linear estimate at 0.72 V. This is a linear estimate for orientation only; real analysis uses libraries at the lowered voltage or a calibrated margin, not this line.
Method | Idea | Cost |
|---|---|---|
Margin in the corner | Characterise the corner at a lower voltage than nominal | Pessimism applied everywhere |
Voltage-aware libraries | Run a scenario at the drooped voltage for affected regions | More libraries and scenarios |
Derate on affected cells | Apply a delay derate to cells in hot regions | Needs a trustworthy droop map |
Slow (setup) corners use nominal minus tolerance and droop, and fast (hold) corners use nominal plus tolerance, each justified against the agreed budget.
The droop budget comes from power analysis and is reviewed when the floorplan or activity changes.
Low-voltage scenarios get the closest review, because a droop costs most nanoseconds there.
The absolute delay-versus-voltage slope is smaller at high voltage (2.25 against 3.75 per volt in the example), and the base delay is smaller too, so the same voltage change moves delay less in ns. Fractionally the sensitivities are almost the same: about 2.9 per volt at 0.72 V against about 2.7 per volt at 0.88 V.