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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
    • Corner and Mode Matrix Design
    • Library Sets and Operating Conditions
      • Library Sets
      • Operating Conditions
      • RC Corner Mapping
      • Temperature Inversion
    • Signoff vs Implementation Views
    • MMMC Debug Playbook
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Library Sets and Operating Conditions
  1. Topics
  2. Static Timing Analysis
  3. Multi-Corner Multi-Mode Signoff
  4. Library Sets and Operating Conditions
  5. RC Corner Mapping

Part 5 · Multi-Corner Multi-Mode · All levels

RC Corner Mapping

Interconnect corners scale wire resistance and capacitance differently; which one is worst depends on whether the net is driver-dominated or wire-dominated.

On this page

    Why it matters

    Wires have resistance and capacitance that vary with manufacturing, and they vary in opposite directions: a wider wire has lower resistance and higher capacitance to neighbours. Extraction therefore provides several interconnect corners, and the worst one depends on the net.

    The four usual corners

    Corner

    Meaning

    Usually used for

    cworst

    Maximum capacitance (resistance low)

    Setup on driver-dominated nets

    cbest

    Minimum capacitance (resistance high)

    Hold on driver-dominated nets

    rcworst

    Maximum resistance-capacitance product

    Setup on wire-dominated nets

    rcbest

    Minimum resistance-capacitance product

    Hold on wire-dominated nets

    example.py
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    corners = {"cworst": (0.90, 1.20), "cbest": (1.10, 0.80), "rcworst": (1.25, 1.05), "rcbest": (0.80, 0.95)}   # (R scale, C scale)
    R0, C0 = 800.0, 120.0              # ohm, fF (illustrative route)
    def delay_ps(driver_ohm, name):
        kr, kc = corners[name]
        return 0.69 * (driver_ohm + R0 * kr) * (C0 * kc) / 1000.0    # lumped estimate, fs -> ps
    def extremes(driver_ohm):
        d = {n: delay_ps(driver_ohm, n) for n in corners}
        return max(d, key=d.get), min(d, key=d.get)
    assert extremes(200.0) == ("rcworst", "rcbest")     # strong driver: wire resistance matters
    assert extremes(3000.0) == ("cworst", "cbest")      # weak driver: load capacitance matters
    print("PASS: strong driver worst/best", extremes(200.0), "; weak driver worst/best", extremes(3000.0))

    With a 200 Ω driver the wire's own resistance exceeds the driver's, so the RC-product corners are the extremes. With a 3000 Ω driver the delay is dominated by charging the capacitance, so the capacitance corners are. The lumped formula is a simplification used only to show the ordering; the extraction tool's results are the real numbers.

    What the review looks for

    • Setup uses the worst of the capacitance and RC-product corners; hold uses the best of both.

    • Neither pair is dropped without evidence that one dominates every net of interest.

    • The same extraction version and the same corner definitions feed implementation and signoff.

    Common pitfall

    Using only the capacitance corners because they are the familiar pair. Long, resistive routes with strong drivers are worst in the RC-product corners.

    Interview

    Explain driver-dominated versus wire-dominated nets in one sentence.

    Check yourself Which corner family is more likely to matter for a short net driven by a weak cell?

    The capacitance corners (cworst, cbest): the delay is set by the load capacitance seen by the weak driver, and the wire's resistance is small.

    Related topics

    • Operating Conditions

    • Next: Temperature Inversion

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    See also

    • Library Sets