A chip must work across process variation, supply voltage, temperature, interconnect variation and every operating mode it ships with. Timing analysis therefore runs many scenarios, each a combination of a corner and a mode, and signs off on the worst of them for each check. This topic covers why corners exist, how the matrix is built, how scenarios are pruned without losing coverage, and how to find which scenario dominates which endpoint.
Lesson | After it you can... |
|---|---|
Explain why setup and hold have different worst corners. | |
Count scenarios and choose which to run for each check. | |
Remove scenarios with a stated tolerance. | |
Find which scenario owns each endpoint. |
Setup is worst where delays are largest and hold where they are smallest, so no single corner covers both; modes add different clocks and constraints; and interconnect corners affect cells and wires differently.