The full matrix of modes, process-voltage-temperature corners and interconnect corners is large. Teams do not run all of it for every check; they pick, for each check type, the scenarios that can be worst. Counting the matrix makes the cost visible and the selection rule explicit.
modes = ["func", "scan_shift", "scan_capture", "mbist"]
pvt = ["ss_0p72v_125c", "ss_0p72v_m40c", "tt_0p80v_25c", "ff_0p88v_125c", "ff_0p88v_m40c"]
rc = ["cworst", "cbest", "rcworst", "rcbest"]
full = [(m, p, r) for m in modes for p in pvt for r in rc]
assert len(full) == 80
# starting plan: setup uses slow PVT with the two worst RC corners; hold uses fast PVT with the two best RC corners
setup = [(m, p, r) for (m, p, r) in full if p.startswith("ss") and r in ("cworst", "rcworst")]
hold = [(m, p, r) for (m, p, r) in full if p.startswith("ff") and r in ("cbest", "rcbest")]
assert len(setup) == 16 and len(hold) == 16
assert not set(setup) & set(hold)
assert len(setup) + len(hold) == 32
print("PASS: full matrix", len(full), "; starting plan", len(setup), "setup +", len(hold), "hold =", len(setup) + len(hold))The full matrix has 4 modes × 5 conditions × 4 interconnect corners = 80 scenarios. The starting plan above runs 16 slow-corner scenarios for setup and 16 fast-corner scenarios for hold, 32 in all. It is a starting guideline, not a rule: hold at slow corners and setup at fast corners can matter for clock-path variation, for hold at low voltage, and for modes with unusual clocking, so teams add scenarios when analysis shows they are needed. Note that the starting plan omits the fast low-voltage corners and the typical condition, which the temperature-inversion lesson says to add per voltage.
Mode | What differs | Typical constraint difference |
|---|---|---|
Functional | Normal operation | Functional clocks, input and output delays, case values at their functional settings |
Scan shift | Test data shifts through chains | Slow scan clock; scan enable constant at 1 through case analysis |
Scan capture | Test response captured | Scan enable 0; at-speed clocks for delay test |
Memory test | Built-in self test of memories | Test clock; memory test controller active |
# not-run: SDC is not executable here
# one mode's constraints: scan shift
create_clock -name scan_clk -period 100 [get_ports scan_clk]
set_case_analysis 1 [get_ports scan_enable]Each mode loads its own constraint file; the corner supplies the libraries and conditions and the interconnect corner supplies the extraction. A scenario is the triple of mode, process-voltage-temperature corner and interconnect corner, and its name should say all three.
The matrix, the starting plan and every addition to it are written down with a reason.
Every mode has a constraint file that was reviewed against that mode's intent.
Scenario names encode mode, PVT and RC corner, and are the same in every report.
From 4 × 5 × 4 = 80 to 5 × 6 × 4 = 120 scenarios, an increase of 40 (50%).