DenseChip

STA Mastery · All levels

STA Interview Q&A Bank

Cross-topic senior STA questions and answer patterns.

Q&A Bank

Explain setup vs hold and which analysis (max vs min delay) applies.

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Q: Explain setup vs hold and which analysis (max vs min delay) applies.

A strong answer names corner/mode/view, path group, metric, artifact, ECO, and regression.

Trap: tool commands without mechanism.

How do you debug WNS regression when netlist is unchanged?

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Q: How do you debug WNS regression when netlist is unchanged?

A strong answer names corner/mode/view, path group, metric, artifact, ECO, and regression.

Trap: tool commands without mechanism.

OCV vs AOCV — when does depth sensitivity matter?

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Q: OCV vs AOCV — when does depth sensitivity matter?

A strong answer names corner/mode/view, path group, metric, artifact, ECO, and regression.

Trap: tool commands without mechanism.

What is your ECO order when setup and hold both fail?

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Q: What is your ECO order when setup and hold both fail?

A strong answer names corner/mode/view, path group, metric, artifact, ECO, and regression.

Trap: tool commands without mechanism.

How do you design an MMMC signoff matrix for a new chip?

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Q: How do you design an MMMC signoff matrix for a new chip?

A strong answer names corner/mode/view, path group, metric, artifact, ECO, and regression.

Trap: tool commands without mechanism.

Q&A drill guide

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CONSTRAINT -> VIEW -> PATH -> METRIC -> ECO -> REGRESSION

Sketch while answering

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constraints -> graph -> slack

Key takeaways

  • State corner, mode, view, and database tag with every slack claim.

  • Run setup and hold plus MMMC regression after every ECO.

Common pitfalls

  • Comparing STA runs with different SPEF or SDC tags.

  • Broad false_path to green-wash violations.

  • Setup-only ECO without hold check.

Practice this lesson