Interviewer is testing

whether you know that one removes a check and the other relaxes it.

Bad answer

"Both tell the tool to ignore the path."

Better answer

"A false path is not timed at all. A multicycle path is timed, but against a later capture edge."

Strong answer (a 4)

Adds the risk of each (a false path can hide a real violation; a multicycle can relax setup beyond what the design supports), that a multicycle setup needs a hold counterpart, and the evidence: a count of paths covered by each exception and a reason that holds for every one.

Follow-ups

When is a false path legitimate? How do you scope it?

Common trap

Using a false path to remove a violation you do not understand.

Evidence to cite

Exception register with path counts.

Taught in

False Paths, Multicycle Paths

Interviewer is testing

whether you know how the hold edge is derived.

Bad answer

"Because hold is also a check."

Better answer

"By default the hold check follows the setup capture edge, so relaxing setup by N cycles also moves hold out by N-1 cycles, which is too strict."

Strong answer (a 4)

Computes it: period 4.0 ns, minimum delay 1.0 ns, hold 0.1 ns: default hold slack +0.9 ns; setup 2 without a hold exception gives 1.0 - (4.0 + 0.1) = -3.1 ns; adding hold 1 restores +0.9 ns. States the rule N-1 for same-clock paths and names the symptom (a hold violation of about a period on a path that was fine).

Follow-ups

What if the clocks differ? What does -end do?

Common trap

Fixing the resulting hold violation with delay cells.

Evidence to cite

Hold slack before and after the exception pair.

Taught in

Forgotten Multicycle Hold

Interviewer is testing

whether you know that the relationship to the source matters.

Bad answer

"A generated clock is any clock you do not want to define."

Better answer

"It declares the clock's source, divide or multiply ratio and sense, so the tool propagates edges and latency from the source and treats the two as related."

Strong answer (a 4)

Adds that defining a divider output as an independent clock loses the relationship and either breaks the analysis or invites a false path; that a missing definition leaves the registers behind unconstrained (a coverage count finds it); and that inversion must be stated or half-cycle paths look like full-cycle ones.

Follow-ups

How do you check clock propagation? What about a clock mux?

Common trap

Treating a divider output as a new unrelated clock and then adding a false path.

Evidence to cite

Registers-per-clock report, with none unclocked.

Taught in

Create Generated Clock, Missing Clock, Wrong Clock Edges

Interviewer is testing

whether you see them as a model of the outside world.

Bad answer

"They add delay to ports."

Better answer

"Input delay is the time after a clock edge that external data arrives at the port; output delay is the time the external capture logic needs before its clock edge."

Strong answer (a 4)

Gives numbers: input delay 2.0 ns on a 5.0 ns clock with a 1.8 ns internal path and 0.10 ns setup leaves +1.10 ns; output delay 1.2 ns with a 2.3 ns internal path on a 4.0 ns clock leaves +0.50 ns. Adds that the delays are relative to a named clock (often a virtual one), and that the interface contract should be reviewed with the other side.

Follow-ups

What is a virtual clock? How do you set min input delays?

Common trap

Setting input delays to zero to make ports pass.

Evidence to cite

Interface budget table agreed with the neighbouring block.

Taught in

Input and Output Delay

Interviewer is testing

whether you measure coverage.

Bad answer

"I review them by eye."

Better answer

"I count the paths each exception covers and compare with what I expected."

Strong answer (a 4)

Describes the audit: exception register with owner, reason and path count; scoped exceptions with through-points rather than whole-clock from and to; rerun with the exception removed to see what comes back; a gate that triggers review when coverage exceeds a multiple of the expected count (1,120 paths against an expected 2 would fire at once).

Follow-ups

What if a legitimate exception covers many paths? How do you review old ones?

Common trap

Trusting an exception because it came from a reviewed project.

Evidence to cite

Exception coverage report and a rerun without the exception.

Taught in

Exception Audit

Interviewer is testing

whether you know that case analysis fixes logic values and disables paths.

Bad answer

"It sets a signal to a value in simulation."

Better answer

"It declares a constant on a pin or port, so the tool propagates it and ignores paths that cannot toggle in that mode."

Strong answer (a 4)

Explains that modes are defined by case values (scan enable 1 in shift mode, a mux select fixed in another), that the constants propagate through logic and select clock mux inputs, that the same value must not be applied in all modes, and that case analysis is not a substitute for a false path between modes. Evidence: the list of disabled arcs and active clocks per mode.

Follow-ups

What if a case value conflicts with a clock definition?

Common trap

Setting a case value globally to simplify a single mode.

Evidence to cite

Active clocks and disabled arcs per mode.

Taught in

Case Analysis and Disable Timing