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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
    • Constraint Bug Patterns
      • Missing Clock
      • Wrong Clock Edges
      • Overbroad False Path
      • Forgotten Multicycle Hold
    • View Mismatch Triage
    • Path Group War Room
    • Signoff Regression Hygiene
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Constraint Bug Patterns
  1. Topics
  2. Static Timing Analysis
  3. STA Debug Playbook
  4. Constraint Bug Patterns
  5. Forgotten Multicycle Hold

Part 9 · Debug Playbook · All levels

Forgotten Multicycle Hold

A multicycle setup relaxation also moves the hold check unless it is corrected; forgetting the hold side produces a large hold violation.

On this page

    Why it matters

    A multicycle setup of N cycles gives the data N periods to arrive. By default the hold check is derived from the setup capture edge, so it moves too: the data must now stay stable until N-1 periods after the launch. For a path that is only slow, not delayed, that requirement is far larger than its real minimum delay. The fix is a separate hold exception.

    Worked example (ns, same clock launch and capture)

    example.py
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    T, min_delay, hold = 4.0, 1.0, 0.1
    hold_default = min_delay - hold                        # hold checked at the launch edge (no multicycle)
    hold_setup_only = min_delay - (T * 1 + hold)           # setup 2 without a hold exception: hold edge one period later
    hold_fixed = min_delay - hold                          # setup 2 plus hold 1: hold edge restored to the launch edge
    assert round(hold_default, 3) == 0.9
    assert round(hold_setup_only, 3) == -3.1
    assert round(hold_fixed, 3) == 0.9
    print("PASS: hold slack default", round(hold_default, 3), "; multicycle setup only", round(hold_setup_only, 3), "; with the hold exception", round(hold_fixed, 3))
    Diagram
    # not-run: SDC is not executable here
    set_multicycle_path 2 -setup -from [get_clocks clk] -to [get_pins u_slow/*/D]
    set_multicycle_path 1 -hold  -from [get_clocks clk] -to [get_pins u_slow/*/D]

    With only the setup exception, hold slack becomes -3.1 ns: the check now wants the data to stay put for a whole extra period. Adding the hold exception with a value of N-1 (here 1) moves the hold edge back to the launch edge and restores the 0.9 ns slack. The unusual signature, a hold violation of about a period on paths that were fine, is how this bug is found. The opposite bug is also dangerous: adding a hold exception with too large a value relaxes the check beyond what the design allows.

    What the review looks for

    • Every multicycle setup exception has a matching hold exception, or a written statement of why not.

    • Hold values are N-1 for same-clock paths unless the design needs another value; the reason is in the exception record.

    • Hold slack on multicycle paths is compared with the pre-exception value: a change of about a period is the bug.

    Common pitfall

    Fixing the large hold violation with delay cells. The violation is a constraint artefact; inserting several nanoseconds of delay would break the design.

    Interview

    Give the pair: setup N, hold N-1, and explain why.

    Check yourself For a 3-cycle setup on the same clock, what should the hold exception value be?

    2 (N - 1): it moves the hold check back by two periods to the launch edge.

    Related topics

    • Overbroad False Path

    • RTL: Multicycle and False Paths

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    See also

    • Missing Clock
    • Wrong Clock Edges