The most dangerous timing bugs do not produce violations. They produce reports that look clean because the constraints removed or relaxed something that should have been checked. Each of the four patterns here has a signature in the numbers and a short test that finds it.
Lesson | After it you can... |
|---|---|
Count unclocked registers and fix the definition. | |
Spot a half-cycle path modelled as a full cycle. | |
Measure what an exception really removed. | |
Fix the hold side of a multicycle setup. |
The constraint basics are in Constraints and SDC; the exception rules are summarised in Multicycle and False Paths.
Each removes checks or loosens them: no clock means no check, a wrong edge widens the budget, a broad false path deletes paths, and a multicycle without hold changes the hold edge. Fewer or looser checks mean fewer violations.