A register-based divider (a flop whose clock-to-Q generates the divided clock) or another clock-generating sequential element can hide a clock from the analysis if no generated clock is defined at its output. The registers behind it are then unconstrained: they have no setup or hold check, and nothing in the violation list tells you. A coverage count reveals the gap. Combinational gates and muxes in the clock network propagate the clock (unateness handled by the analysis), but their gating checks and mux-select relationships must still be checked.
registers = {"clk_a": 4200, "clk_b": 1800, "(no clock)": 600} # registers by the clock that reaches them
total = sum(registers.values())
unclocked = registers["(no clock)"]
assert total == 6600
share = unclocked / total
assert round(share * 100, 1) == 9.1
# after defining the divided clock at the divider output
after = {"clk_a": 4200, "clk_b": 1800, "clk_div2": 600}
assert sum(after.values()) == total and "(no clock)" not in after
print("PASS:", unclocked, "of", total, "registers (", round(share * 100, 1), "% ) had no clock before the fix; 0 after")# not-run: SDC is not executable here
create_clock -name clk_a -period 2.0 [get_ports clk_a]
create_generated_clock -name clk_div2 -source [get_ports clk_a] -divide_by 2 [get_pins u_div/q_reg/Q]600 of 6600 registers (9.1%) had no clock, and WNS and TNS reflected only the other 90.9%. Defining the divided clock at the divider's output pin brings them into the analysis. The clock definition names the source and the divide ratio; it does not make the divider itself behave, and the divider's own register is still a normal clocked element on clk_a. The check to run every time is a report of registers without a clock (and of clock pins without a defined clock); it should be empty.
Unclocked registers and unclocked clock pins: counts are zero, or each exception is listed with a reason.
Every sequential divider or other clock-generating sequential element in the clock network has a generated clock defined at its output; combinational gates and muxes propagate the clock, and their gating checks and mux-select relationships are checked.
The count of timing endpoints is compared with the count of registers and ports, and differences are explained.
It can only stay the same or get worse: the 600 newly checked registers add paths, some of which may fail.