Why it matters

The capture edge decides how much time a path gets. A flop on the falling edge of a clock gets half a period from a rising-edge launch. If the clock reaching it is modelled with the wrong sense, for example a clock redefined on an inverted net without the inversion flag, or a sequential divider output that is really inverted but is defined as non-inverted, the analysis picks the wrong edge and the path looks easier than it is. A plain combinational inverter needs no definition of its own: it inverts the propagated clock automatically, so the half-cycle capture is inferred.

Worked example (ns)

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T, setup, delay = 2.0, 0.08, 1.10
slack_correct = T / 2 - setup - delay          # launch on rising edge, capture on the falling edge half a period later
slack_wrong = T - setup - delay                # inverted clock modelled as non-inverted: next rising edge, a full period
assert round(slack_correct, 3) == -0.18
assert round(slack_wrong, 3) == 0.82
assert round(slack_wrong - slack_correct, 3) == T / 2
print("PASS: correct slack", round(slack_correct, 3), "; wrongly modelled slack", round(slack_wrong, 3), "; optimistic by", T / 2)

# not-run: SDC is not executable here
# correct: the clock redefined on the inverted net carries the inversion flag
create_generated_clock -name clk_n -source [get_ports clk] -divide_by 2 -invert [get_pins u_div/qn_reg/QN]

The real path has -0.18 ns of slack: a violation. With the clock sense lost the same path shows +0.82 ns, optimistic by exactly half a period. The signature is a half-cycle path in the schematic (a falling-edge flop, an inverted clock net) with a full-period requirement in the report, tracing back to a clock redefined on the inverted net without the inversion flag, or to a sequential divider's inverted output defined as non-inverted. The inversion flag on the redefined clock restores the right capture edge. For a flop that is itself falling-edge triggered, the analysis infers the edge from the cell, so the bug lives in clock definitions, not in such cells.

What the review looks for

• Every clock redefined on an inverted net carries the inversion flag, and every sequential divider output is checked for sense and ratio; plain combinational inverters propagate the clock automatically and need no clock of their own.

• A report of paths between opposite-edge clocks is reviewed: half-cycle paths should appear with half-period requirements.

• The capture edge printed in a path report is compared with the schematic for every suspicious path.

Related topics

• Missing Clock

• Next: Overbroad False Path