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Course contents

  • How to Use This Course
  • Reading Path
  • STA Glossary
  • STA Metrics Reference
  • STA Mastery Cheatsheet
  • Timing Paths and Checks16
  • Constraints & SDC Fundamentals20
  • Delay Graph & Path Analysis16
  • Beyond Setup and Hold16
    • Latches and Time Borrowing
      • Latch Timing Model
      • Time Borrowing Worked
      • Borrowing Chains
      • Latch Signoff Rules
    • Clock Gating Checks
    • Recovery, Removal and Async
    • Pulse Width and Min Period
  • Multi-Corner Multi-Mode Signoff16
  • OCV, AOCV, POCV and Variation16
  • Crosstalk and Noise16
  • ECO and Closure16
  • STA Debug Playbook16
  • STA Interview Prep26
  • Capstone Timing Signoff Lab4
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‹Beyond Setup and Hold
  1. Topics
  2. Static Timing Analysis
  3. Beyond Setup and Hold
  4. Latches and Time Borrowing

Part 4 · Beyond Setup and Hold · All levels

Latches and Time Borrowing

How level-sensitive latches are timed, how data arriving after the latch opens borrows time from the next stage, and the rules for signing it off.

  • 4topics
  • 4lessons

A flop captures at an instant; a latch is transparent for a whole phase of the clock. That difference lets a late-arriving signal pass through and use time that would have belonged to the next stage. Timing analysis models this as time borrowing. This topic covers the latch timing model, a worked borrowing example, chains of borrowing, and the signoff rules.

Lesson

After it you can...

Latch Timing Model

Name the opening and closing edges and the checks at each.

Time Borrowing Worked

Compute borrowed time and its effect on the next path.

Borrowing Chains

Follow borrowing through several latches.

Latch Signoff Rules

Apply the review rules for latch-based paths.

Check yourself What is the maximum a latch can borrow?

The transparent window minus the setup time to the closing edge: data must arrive before the latch closes (less setup), and the borrowed time is whatever it arrives after the opening edge. The usable borrow is the smaller of that window limit and the downstream slack.

Interview

Contrast flop and latch in one sentence each: the flop samples at an edge, the latch passes data during a phase, so late data can borrow time from the next stage.

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See also

  • Clock Gating Checks
  • Recovery, Removal and Async
  • Pulse Width and Min Period