Latches appear in hand-crafted datapaths, clock gating cells, and some synchronisation structures. Their timing is not a single capture instant, so reports speak about time borrowed and time given. Reading them requires the three-edge view: the opening edge, the closing edge, and the transparent time between.
Term | Meaning (positive-level latch) |
|---|---|
Opening edge | The clock rising edge: the latch becomes transparent |
Closing edge | The clock falling edge: the latch holds the value |
Transparent window | The high phase: duration = pulse width (50% of the period for a symmetric clock) |
Setup check | Data must arrive before the closing edge less setup time |
D to Q | While transparent, the output follows D after the latch's delay |
Hold check | Data must not change just after the closing edge |
# Positive latch, period 10 ns, 50% duty: opens at 0, closes at 5. Setup 0.1.
open_edge, close_edge, setup = 0.0, 5.0, 0.1
window = close_edge - open_edge
max_arrival = close_edge - setup
assert window == 5.0 and abs(max_arrival - 4.9) < 1e-9
# a signal arriving at 3.2 passes through transparently: it borrows 3.2 ns from the next stage
arrival = 3.2
borrowed = max(0.0, arrival - open_edge)
assert abs(borrowed - 3.2) < 1e-9 and arrival <= max_arrival
print("PASS: transparent window", window, "ns; maximum arrival", round(max_arrival, 2), "ns; borrowed", borrowed, "ns")The window is 5 ns; data may arrive up to 4.9 ns after the opening edge. A signal arriving 3.2 ns after the opening edge simply passes through, and downstream timing starts from 3.2 ns (plus the D-to-Q delay), not from the opening edge. That is borrowing: the next stage has 3.2 ns less than it would if the latch were an edge-triggered flop at the opening edge. A positive-level latch fed by a rising-edge flop on the same edge is a same-phase relationship: its capture is the next opening edge, not the opening edge it shares.
Every latch is intentional and listed; unintended latches from RTL (incomplete assignments) are design errors found by lint.
Transparent window and duty cycle are in the clock definition; asymmetric duty changes the borrowing limit.
The report distinguishes the opening-edge path (no borrowing) from the borrowing case.
3 ns (30% of the period), so the latest data arrival is 3 ns after opening less the setup time.