Request transition and block new transactions.
Drain or checkpoint outstanding work; acknowledge quiescence.
For frequency increase, raise voltage before frequency; for decrease, lower frequency before voltage.
Switch/divide clock through approved hardware and wait for stable/lock indication.
Select the matching timing/voltage mode and release reset if the domain was reset.
Resume traffic and log completion or timeout.
Read each panel left to right. The shaded columns are the start and end of the protocol; the two middle columns are the only places where voltage or frequency moves.
Both directions start by quiescing and end by resuming: the change itself never happens under live traffic.
Going faster, the voltage step comes first, so the cells are already fast enough when the clock speeds up.
Going slower, the frequency step comes first, so the clock is already slow when the cells slow down.
In the worked tree, the power manager moves the core between the signed-off 400 MHz nominal scenario and a lower-frequency, lower-voltage scenario. Hardware selects operating state at runtime; STA separately signs off an analysis view for every legal state.
Failure | Containment |
|---|---|
Quiesce timeout | Abort transition and report blocking owner |
PLL does not lock | Keep domain reset/isolated; fall back to safe clock |
Voltage acknowledgement missing | Do not increase frequency |
Clock loss during transition | Assert containment and restart sequence |
CDC peer remains active | Handshake at boundary or isolate before clock change |
Higher frequency requires faster cell delay, which depends on sufficient voltage. Increasing frequency first can violate timing before the voltage reaches its new level.