In a source-synchronous interface, the transmitter sends data and a clock/strobe together. The receiver captures relative to that forwarded clock, not the chip's unrelated system clock.
The worked interface receives eight data bits beside rx_strobe_i. IO cells capture the bus in the strobe domain, then an elastic buffer transfers complete beats into the 400 MHz core without treating the strobe as synchronous to the PLL.
Concern | RTL/constraint response |
|---|---|
Launch relationship | Register data and forwarded clock from controlled source logic |
Board/package skew | Input/output delay min/max around forwarded clock |
DDR | Capture both edges with approved IO cells |
Deskew | Delay training or phase adjustment where required |
Transfer to core | Elastic buffer or CDC after the IO capture domain |
Keep the high-speed capture in the IO/forwarded-clock domain. Cross into the core using a documented FIFO or handshake rather than pretending the clocks are synchronous.
Illustrative assumptions, all times in ns at the receiver pins: an 8.00 ns strobe launches data on its falling edge at 4.00 and captures on the next rising edge at 8.00. External clock-to-data plus data-minus-strobe board/package skew gives arrival offsets of 0.35 to 2.10 ns relative to the falling strobe at the pin. Assume an ideal pin-to-capture path for this paper budget, setup 0.20, hold 0.10 and relative uncertainty 0.15 for each check. Internal IO/data/clock insertion delays must be included by STA in the actual design.
Read the picture left to right along the time axis. The hatched areas are when the data may be changing; the shaded area is when the current beat is guaranteed stable.
The data finishes changing at 6.10 (4.00 + 2.10) and the next beat cannot start changing before 12.35 (12.00 + 0.35).
The capture edge at 8.00 sits inside the stable region, but the check is against the two boundaries: 7.65 for setup and 8.25 for hold.
Setup margin is the gap from 6.10 to 7.65, which is 1.55 ns. Hold margin is the gap from 8.25 to 12.35, which is 4.10 ns.
The margins are paper numbers from the assumptions above, not measured slack.
Paper check | Calculation / illustrative margin |
|---|---|
Setup | 8.00 - 0.20 - 0.15 - (4.00 + 2.10) = 1.55 ns |
Hold | (12.00 + 0.35) - (8.00 + 0.10 + 0.15) = 4.10 ns |
Boundary | All eight bits must satisfy both bounds; nominal bus arrival is insufficient |
These arithmetic margins are assumptions, not measured slack or physical signoff. DDR needs separate rising/falling budgets; deskew changes the edge relationship and must be reflected in constraints. The forwarded strobe closes pin-to-IO capture timing only. Subsequent complete-beat transfer into the unrelated core needs CDC/FIFO analysis, not a setup budget against the core PLL. The constraint example uses this same falling-launch/rising-capture contract.
The strobe captures pins in its own timing domain; the FIFO absorbs phase/frequency differences and safely transfers data into the core clock domain.
The SDR numbers are paper assumptions: ideal pin-to-capture path, setup 0.20, hold 0.10 and relative uncertainty 0.15. They are not measured slack or physical signoff, and STA must add the internal IO, data and clock insertion delays.